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# Micro-architect/Logic Designer, Coherent Interconnect in San Jose

- **Company:** Energy Jobline
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $151,000.0
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Network Topologies, Static Timing Analysis, Verilog, Network Switches, Application Specific Integrated Circuits, Caching, Information Technology
- **Published:** August 4, 2026
- **Apply:** https://www.energyjobline.com/job/micro-architect-logic-designer-coherent-interconnect-san-jose-31337746

## About the Role

* 10+ years of experience with a Bachelor's degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master's degree, or 6+ years of experience with a PhD
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 * Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs
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 * Demonstrated successful architectural through RTL design experience on high performance digital designs
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 * Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
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 * Knowledge of system caches and directory snoop filter protocols.
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 * Familiarity with different on-chip network topologies: mesh, ring, crossbar.
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 * Experience in leading and mentoring a team of engineers.
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 * Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols
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 * Knowledge of memory subsystem design including coherent cache design.
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 * Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.
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