> Markdown version of [/jobs/ext/266232-senior-design-engineer](https://www.wearedevelopers.com/jobs/ext/266232-senior-design-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior Design Engineer - **Company:** Micron Technology, Inc. - **Location:** San Jose, CA, United States - **Experience:** Expert - **Salary:** $116,000.0 - $198,000.0 - **Contract:** Permanent contract - **Skills:** Computer Engineering, Non-Volatile Memory, Verilog - **Published:** May 19, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=5c96a4e7329def8d ## About the Role * Bachelor's degree in Computer Engineering or Electrical Engineering * 5+ years of experience in digital circuit design and development. * Proven track record to meet performance, area, and power targets. * Experience with RTL and gate-level verification processes. * Strong collaboration skills with multi-functional teams., * Master's degree or Ph.D. in Computer Engineering or Electrical Engineering * Experience in technical leadership or project management roles. * Knowledge of non-volatile memory technologies, particularly NAND. * Familiarity with building architecture and verification guidelines. * Excellent documentation and training skills. ## Description As a Senior Design Engineer at Micron, you will play a pivotal role in highly technical teams! You will be responsible for crafting and analyzing digital circuits used in memory product development. This role demands technical expertise and leadership to efficiently implement and optimize NAND circuits. You will collaborate with various internal and external teams to ensure our products meet high standards of performance, quality, and reliability!, * Interpret device and system specifications to deliver required functionalities * Participate in the conception and development of new circuits * Define and design composition architecture specifications for new features. * Support the creation of schematics and/or RTL blocks * Define best known design and verification practices and communicate them to the department * Perform RTL and synthesized netlist (gate level) verification at block, subsystem, and fullchip level * Facilitate netlist bring up to achieve basic functionality * Responsible for delivering design simulation including post layout * Design verification plans for new and existing features and check desired behavior in Verilog * Collaborate with Product Engineering on validation plans and review silicon results * Assist in silicon design validation, reticle experiments, qualification, and tape-out revisions as needed ## Related Videos - [A Brief History of Data Storage](https://www.wearedevelopers.com/videos/974-a-brief-history-of-data-storage) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Swapping a Data Warehouse at Runtime: Zero-Downtime Migration Without Changing a Single Client](https://www.wearedevelopers.com/videos/100311-swapping-a-data-warehouse-at-runtime-zero-downtime-migration-without-changing-a-single-client) - [Agentic AI: building autonomous systems for developers](https://www.wearedevelopers.com/videos/100034-agentic-ai-building-autonomous-systems-for-developers) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) - [AI Agents & Agentic AI](https://www.wearedevelopers.com/videos/2017-ai-agents-agentic-ai) ## Related Articles - [What’s the Difference between a Junior, Mid, and Senior Developer?](https://www.wearedevelopers.com/magazine/238-what-s-the-difference-between-a-junior-mid-and-senior-developer) - [Dev Digest 188: CfP time, the risks of NPM and IKEA algorithms](https://www.wearedevelopers.com/magazine/635-dev-digest-188-cfp-time-the-risks-of-npm-and-ikea-algorithms) - [From developer to manager – what does it take to become an engineering manager?](https://www.wearedevelopers.com/magazine/42-from-developer-to-manager-what-does-it-take-to-become-an-engineering-manager) - [Everything a Developer Needs to Know About MCP with Neo4j](https://www.wearedevelopers.com/magazine/604-everything-a-developer-needs-to-know-about-mcp-with-neo4j) - [Why Attend a Developer Event in 2026?](https://www.wearedevelopers.com/magazine/688-why-attend-a-developer-event-in-2026) - [Should Tech Managers Be Developers First? Pros and Cons](https://www.wearedevelopers.com/magazine/327-should-tech-managers-be-developers-first-pros-and-cons)