> Markdown version of [/jobs/ext/2693593-ddr-design-engineer](https://www.wearedevelopers.com/jobs/ext/2693593-ddr-design-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # DDR Design Engineer - **Company:** Apple Inc. - **Location:** Newton, MA, United States - **Experience:** Experienced - **Salary:** $165,800.0 - **Contract:** Permanent contract - **Skills:** Code Coverage, Digital Arts, Logic Synthesis of Circuits, SystemVerilog, Verilog, State Machines - **Published:** September 3, 2026 - **Apply:** https://www.themuse.com/jobs/apple/ddr-design-engineer-998f41 ## About the Role At Apple, we work every day to craft products that enrich people's lives. If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated DDR Design Engineer., RTL design using Verilog or SystemVerilog, assertion writing. Design of state machines, data paths, arbitration and clock domain crossing logic. Logic synthesis, timing constraints. Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior experience in DDR PHY design and mixed-signal environment is a plus., BS degree in technical discipline with minimum 10 years of relevant experience ## Description In this role, you will be responsible for performing concept studies and providing direction in terms of performance, gate count and power for various digital designs. You will be responsible for writing detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers. You will provide high-quality RTL description, including assertions, for the design. Use formal tools and static checkers to guarantee RTL quality. You will also support design verification to insure bug-free first silicon. Responsibilities will include driving functional and code coverage as well as timing closure for your designs and supporting silicon bring-up, performance and power characterization. ## Related Videos - [How to Domain Model – An example from manufacturing](https://www.wearedevelopers.com/videos/742-how-to-domain-model-an-example-from-manufacturing) - [Mutation Testing and Fuzzing in C#](https://www.wearedevelopers.com/videos/703-mutation-testing-and-fuzzing-in-c) - [Transforming Newspaper Readers into NFT holders](https://www.wearedevelopers.com/videos/1162-transforming-newspaper-readers-into-nft-holders) - [Test-reduction - Doing more with less](https://www.wearedevelopers.com/videos/977-test-reduction-doing-more-with-less) - [WeAreDevelopers LIVE - CSS is DOOMed](https://www.wearedevelopers.com/videos/1851-wearedevelopers-live-css-is-doomed) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) ## Related Articles - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Dev Digest 103 - Superb Owl Trafficking](https://www.wearedevelopers.com/magazine/388-dev-digest-103-superb-owl-trafficking) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Dev Digest 154: Responsible AI? Mistakes of CSS & track all the things!](https://www.wearedevelopers.com/magazine/548-dev-digest-154-responsible-ai-mistakes-of-css-track-all-the-things) - [Dev Digest 118 - not a total recall](https://www.wearedevelopers.com/magazine/452-dev-digest-118-not-a-total-recall) - [Dev Digest 129 - Now that's what I call private data!](https://www.wearedevelopers.com/magazine/468-dev-digest-129-now-that-s-what-i-call-private-data)