> Markdown version of [/jobs/ext/2696238-soc-digital-design-engineer-multimedia-lab](https://www.wearedevelopers.com/jobs/ext/2696238-soc-digital-design-engineer-multimedia-lab). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # SoC Digital Design Engineer, Multimedia Lab - **Company:** The Client - **Location:** San Jose, CA, United States - **Experience:** Expert - **Salary:** $218,400.0 - **Contract:** Permanent contract - **Skills:** Codecs, Software Debugging, Digital Electronics, Logic Synthesis of Circuits, Electronic Design Automation, Perl (Programming Language), Firmware, Field-Programmable Gate Array (FPGA), Make (Software), Hardware Design, Python (Programming Language), Static Timing Analysis, Subsystems, SystemVerilog, Tcl (Programming Language), Verilog, Video Codec, Video Encoding, Scripting, Application Specific Integrated Circuits, Backend, Information Technology, Hardware Acceleration, Front End Software Development, Physical Design - **Published:** September 3, 2026 - **Apply:** https://www.themuse.com/jobs/tiktok/senior-soc-digital-design-engineer-multimedia-lab ## About the Role Bachelor's degree or higher in Microelectronics, Integrated Circuits, Computer Science, Electrical Engineering, or a related field. - 3+ years of experience in digital front-end design (open to highly promising candidates with less experience). - Mastery of Verilog/SystemVerilog and a solid foundation in digital circuits. - Proficiency with mainstream front-end EDA tools (e.g., Spyglass, Design Compiler, PrimeTime). - Fluent in at least one scripting language (Python, Perl, Tcl, Makefile) for workflow automation. Preferred Qualifications: - Deep understanding of NPU architecture, HW/SW co-design and AI hardware acceleration. - Proven experience in SoC-level performance profiling and bottleneck analysis. - Hands-on experience in the integration of complex SoC core subsystems (e.g., CPU/NPU clusters, Memory subsystems). - Successful tape-out experience in advanced process nodes (7nm/5nm/3nm) ## Description About the team: Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve billions of users. We are looking for strong video codec design engineers to design hardware accelerators for advanced video encoding and processing. The successful candidate will be part of a fast-growing team that includes algorithm, architecture, software, firmware, and hardware design and verification experts with a dedication to technical excellence and a passion to build large-scale and high-performing video platforms and services. Responsibilities - Architecture Design: Participate in defining the architecture of SoC top or subsystems (NoC/CPU/NPU/ISP/Codec), and conduct PPA (Power, Performance, Area) evaluation during the early design phase. - RTL Implementation: Write high-quality, well-structured RTL code (Verilog/SystemVerilog) and maintain related design documentation. - Front-End Quality Control: Perform Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks to ensure code standard compliance and design robustness. - Cross-Functional Collaboration: Work closely with the Verification team for debugging and achieving Coverage closure; collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA (Static Timing Analysis), and power optimization. - Low Power Design: Participate in the formulation of chip low-power strategies, proficiently apply Clock Gating and Power Gating techniques, and support the UPF (Unified Power Format) flow. ## Related Videos - [Can You Touch the Internet? A Journey in Remote Touch With Edge Computing and Haptic Coding](https://www.wearedevelopers.com/videos/1463-can-you-touch-the-internet-a-journey-in-remote-touch-with-edge-computing-and-haptic-coding) - [Developing the Backend with Stefan Lingler, CTO at Shpock](https://www.wearedevelopers.com/videos/100360-developing-the-backend-with-stefan-lingler-cto-at-shpock) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) - [WeAreDevelopers LIVE - Building The World’s Worst Image Editor™](https://www.wearedevelopers.com/videos/1836-wearedevelopers-live-building-the-world-s-worst-image-editor) - [Speech-to-Speech AI models - Marius Obert](https://www.wearedevelopers.com/videos/1907-speech-to-speech-ai-models-marius-obert) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) ## Related Articles - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Dev Digest 129 - Now that's what I call private data!](https://www.wearedevelopers.com/magazine/468-dev-digest-129-now-that-s-what-i-call-private-data) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Dev Digest 102 - Race conditions](https://www.wearedevelopers.com/magazine/386-dev-digest-102-race-conditions) - [Top 6 Hackathons for Developers in 2023](https://www.wearedevelopers.com/magazine/263-top-6-hackathons-for-developers-in-2023) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers)