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# Sr. Digital ASIC Design Engineer (TERADYNE, Agoura Hills, CA)

- **Company:** Teradyne Inc.
- **Location:** Agoura Hills, CA, United States
- **Experience:** Expert
- **Salary:** $154,900.0 - $247,800.0
- **Contract:** Permanent contract
- **Skills:** Software Debugging, Logic Synthesis of Circuits, Python (Programming Language), Static Timing Analysis, Tcl (Programming Language), Verilog, Linux Virtual Server, Application Specific Integrated Circuits, State Machines, Physical Design
- **Published:** September 3, 2026
- **Apply:** https://jobs.teradyne.com/talentcommunity/apply/1425698000/?locale=en_US

## About the Role

* BSEE required; MSEE or PhD desired.
 * 8+ years of ASIC or digital design experience with strong expertise in Verilog[DEL: :DEL] RTL development.
 * Proven experience designing complex digital blocks including state machines, FIFOs, high-speed datapaths, arbitration logic and DFT-friendly architectures.
 * Strong knowledge of RTL to Netlist ASIC development flows including synthesis, static timing analysis (STA), clock domain crossing (CDC), and timing closure.
 * Experience integrating third-party and custom IP into large-scale SoCs or mixed-signal ASICs.
 * Experience performing Block level P&R of high-speed digital blocks and interfaces to analog IP
 * Experience with EM/IR analysis
 * Experience with DRC/LVS signoff
 * Proficiency with scripting and automation using Python, Tcl, Make, or similar languages.
 * Experience supporting verification, silicon bring-up, debugging, and root-cause analysis.
 * Strong collaboration, communication, and problem-solving skills with the ability to mentor junior engineers and drive technical excellence across cross-functional teams.

## Description

Teradyne's Digital ASIC Group is seeking a Senior ASIC Digital Design Engineer to help develop complex mixed-signal ASICs for next-generation semiconductor test systems. Working closely with architects, analog designers, verification engineers, and physical design teams, you will drive digital design activities from architecture definition through silicon bring-up. This role offers the opportunity to own critical ASIC subsystems, influence technical direction, and contribute to cutting-edge products in a highly collaborative environment.


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