> Markdown version of [/jobs/ext/2704028-asic-architect](https://www.wearedevelopers.com/jobs/ext/2704028-asic-architect). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # ASIC Architect - **Company:** Intersources Inc. - **Location:** Saratoga, CA, United States - **Salary:** $26,000.0 - **Contract:** Permanent contract - **Skills:** Adobe InDesign, Artificial Intelligence, Ethernet, Firmware, Multi-protocol Systems, Network Control, Network Protocols, PCI Express, Software Requirements Analysis, TCP/IP, Virtual Local Area Networks, Application Specific Integrated Circuits, Parallel Computation, Low Latency, Physical Design, Scheduling Algorithms - **Published:** September 4, 2026 - **Apply:** https://www2.jobdiva.com/portal/?a=62jdnw10t7d77ytz0lbaey9qxonk3b05a9tqw96rb7z6hlfo7xj79l9g6mp6aj2o&compid=0/jobs/31975613#/jobs/31975613 ## About the Role * MSEE with 10+ years of experience, preferably in networking ASIC architecture and design. * Candidates with experience in related areas of computer and parallel processing architectures - in particular, complex memory crossbars, buffering schemes, scheduling algorithms and high-speed datapaths - are also highly desired. * A deep understanding of networking protocols (Ethernet, TCP/IP, UDP, VLAN, MPLS, RoCE, etc.) and their hardware implications, or a willingness to become expert. * Demonstrated expertise in microarchitecture definition, performance modeling, and trade-off analysis. Capability to develop Architecture behavioral models is highly desired. * Experience working across the ASIC development lifecycle, from concept through productization. * Experience in high-speed I/O integration (e.g., PCIe Gen5/Gen6, SerDes) and Software Control Plane interface architecture is highly desirable. * Understanding of physical design implications on packet processing and buffering architecture (e.g., timing, area, power). * Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex issues. Exceptional written and verbal communication skills, including the ability to document and present complex architectural concepts clearly. ## Description We are looking for a highly experienced ASIC Architect to contribute to the definition and implementation of Client's industry leading networking products. This is a unique opportunity to help shape the future of AI Networking., * Work closely with the CTO to translate high-level system requirements and customer use cases into detailed architecture and functional specifications. * Collaborate with chip and system microarchitects to align ASIC architecture with system-level goals for throughput, latency, and power efficiency. * Guide modeling and feasibility analysis of packet flow behavior through the switch datapath to validate architectural choices, including throughput, latency, power and area efficiencies. * Work closely with RTL, Verification, Physical Design and Firmware teams to ensure seamless design implementation and handoff. * Guide integration of internal and external IPs (e.g. MAC, PCIe, SerDes) into the broader architecture. Drive interface requirements. * Participate in design reviews, performance modeling, test and verification strategies and architectural trade-off analysis. * Contribute to post-silicon validation for performance and correctness. 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