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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Staff Design Engineer - **Company:** Impinj - **Location:** United States (Remote available) - **Experience:** Expert - **Salary:** $158,700.0 - $238,100.0 - **Contract:** Permanent contract - **Skills:** Computer-Aided Design, Analog Electronics, Databases, Software Debugging, Radio-Frequency Identification, Cadence Virtuoso, Signal Integrity, Linux Virtual Server, Software Verification - **Published:** September 4, 2026 - **Apply:** https://startup.jobs/senior-staff-design-engineer-ic-layout-impinj-8800221 ## About the Role * Bachelor's or master's degree in computer or electrical engineering or a related technical field, with 12+ years of experience * Experience in custom analog, RF, and mixed-signal layout, with ability to lead complex ICs from conception to tapeout * Versed in tapeout flows with experience in final database preparation and tapeout checklists * Ability to lead and mentor other layout engineers as the top-level floorplan/IC integration owner, partnering with circuit designers to resolve complex problems * Expert in full-chip/SOC-level floorplanning and integration - physical implementation of cells and analog blocks/IPs, pin-ring generation, routing management, and full-wafer assembly - with experience delivering advanced floorplan strategies and debugging DRC/LVS verification across intermediate hierarchies and at the full-chip level, for both analog-on-top (AOT) and digital-on-top (DOT) methodologies * Understanding of semiconductor manufacturing processes and foundry technologies across advanced process nodes down to 16nm for ultra-low-power and high-fidelity applications * Understanding of analog layout challenges and layout-dependent effects in advanced processes - noise coupling, matching, parasitics, LOD, WPE, PSE, and coloring - along with proficiency in mitigation techniques such as guard rings, DNW, PN junctions, parasitic management, signal integrity, reliability (EMIR), and ESD. Expert knowledge of Cadence Virtuoso schematic and layout editors, plus Cadence/Siemens layout verification tools (including PVS and Siemens Calibre DRC/LVS), with strong proficiency interpreting and correcting ERC, DRC and LVS error reports * Strong communication skills to effectively collaborate with cross-functional teams and external partners * Demonstrated strong technical project management skills with the ability to prioritize tasks, anticipate roadblocks, manage schedules, and deliver results in a fast-paced environment ## Description * Leverage Top-Down Bottom-Up (TDBU) floorplan methodology to create and refine the RFID or Reader IC floorplan - collaborating with circuit and block-level layout designers on sizing, pin rings, inter-block routing, and full-chip channels - while maintaining order in layout hierarchy for streamlined development and tape-in * Work closely with the analog and digital design teams on floor planning, pin placement, power supply strategy and signal distribution between blocks * Coordinate with program managers and cross-functional teams - design, verification, packaging, manufacturing, and foundry - to track layout and floorplan activities to a predictable schedule and lead a successful, timely and quality tape-out * Conduct layout reviews for power/ground routing, electromigration, matching, and signal coupling/integrity, and complete full-chip closure activities, including seal-ring and bump integration, dummy fill, DRC, LVS, density, and DFM checks * Perform detailed transistor-level layout of RF, mixed-signal, and analog circuit blocks for both high-performance RF as well as ultra-low power and compact RFID * Participate in the IC layout methodology roadmap, collaborating with technology, CAD, and design teams to ensure successful deployment while balancing short-term execution with long-term strategic goals ## Related Videos - [Angular Signals: what's all the fuss about?](https://www.wearedevelopers.com/videos/684-angular-signals-what-s-all-the-fuss-about) - [Kubernetes and Microservices with Multi-Model Databases](https://www.wearedevelopers.com/videos/382-kubernetes-and-microservices-with-multi-model-databases) - [Engineering/Manager Pendulum: Generating compound interest on your career](https://www.wearedevelopers.com/videos/100348-engineering-manager-pendulum-generating-compound-interest-on-your-career) - [Robust AIGC Provenance with Invisible Watermarking](https://www.wearedevelopers.com/videos/100222-robust-aigc-provenance-with-invisible-watermarking) - [Fault Tolerance and Consistency at Scale: Harnessing the Power of Distributed SQL Databases](https://www.wearedevelopers.com/videos/1146-fault-tolerance-and-consistency-at-scale-harnessing-the-power-of-distributed-sql-databases) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) ## Related Articles - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [Top Characteristics of a Software Engineer](https://www.wearedevelopers.com/magazine/166-top-characteristics-of-a-software-engineer) - [Fully Remote Software Engineer Jobs](https://www.wearedevelopers.com/magazine/447-fully-remote-software-engineer-jobs) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [What is Software Engineering?](https://www.wearedevelopers.com/magazine/289-what-is-software-engineering) - [From developer to manager – what does it take to become an engineering manager?](https://www.wearedevelopers.com/magazine/42-from-developer-to-manager-what-does-it-take-to-become-an-engineering-manager)