> Markdown version of [/jobs/ext/2708189-principal-lead-dsp-systems-architect-ultra-high-speed-serdes](https://www.wearedevelopers.com/jobs/ext/2708189-principal-lead-dsp-systems-architect-ultra-high-speed-serdes). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Principal / Lead DSP & Systems Architect - Ultra High-Speed SerDes - **Company:** Omni Design Technologies, Inc. - **Location:** United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Algorithm Design, Learning Management Systems, Microarchitecture, Software Debugging, Ethernet, Python (Programming Language), MATLAB, Signal Processing, Systems Architecture, IEEE 802.3 - **Published:** September 4, 2026 - **Apply:** https://startup.jobs/principal-lead-dsp-systems-architect-ultra-high-speed-serdes-omni-design-technologies-8657714 ## About the Role * Graduate degree in EE, Communications, or Signal Processing; PhD strongly preferred. * 10+ years in high-speed SerDes or wireline/optical link DSP/systems architecture, with direct exposure to 112G/224G silicon and a clear path into 448G and beyond across electrical and optical interfaces. * Proven ownership of end-to-end link budgets with cascaded impairment analysis across channel (electrical and/or optical), AFE, ADC/DAC, DSP, and FEC. * Deep expertise in: PAM4/PAM6 and coherent wireline/optical signaling; advanced equalization (FFE, DFE, MLSE/MLSD, Tomlinson-Harashima); optical DSP (CD/PMD compensation, polarization recovery, carrier phase/frequency recovery) for candidates with optical exposure; adaptive algorithms and link training; KP4 and soft-decision FEC; high-speed ADC/DAC architectures (time-interleaved, calibration, ENOB-driven design); CDR and timing recovery at multi-hundred-Gbaud rates; jitter/crosstalk/SI and optical impairment modeling; fixed-point DSP and bit-true modeling; MATLAB/Python link simulation; DSP-to-RTL methodology. * Familiarity with OIF CEI (CEI-224G, CEI-448G), IEEE 802.3 high-speed Ethernet, and relevant optical standards (e.g., OIF coherent agreements, IEEE 802.3 optical PHYs). * Track record of defining specs consumed by RTL, DSP, mixed-signal, verification, and validation teams. * Strong communication skills with VP- and CTO-level stakeholders at hyperscale and module customers. ## Description We are seeking a Principal / Lead DSP & Systems Architect to own the architectural direction of ultra high-speed SerDes platforms targeting 448G per lane and emerging post-448G standards, spanning both electrical (chip-to-chip, backplane, copper cable) and optical (IM-DD and coherent) interfaces. This individual will drive end-to-end link architecture, DSP algorithm design, and ADC/DAC-based transceiver partitioning, serving as the primary technical interface with strategic customers and standards bodies. The ideal candidate combines deep expertise in high-speed link theory, advanced equalization and FEC, PAM/multi-level and coherent signaling, and hardware-aware DSP implementation, with a track record of delivering SerDes IP into silicon at the bleeding edge of the wireline and optical roadmap., Architecture & Roadmap: Define DSP and system architecture for 448G and post-448G SerDes IP across electrical and optical interfaces - including ADC/DAC-based transceiver partitioning, modulation choice (PAM4/PAM6, IM-DD, coherent), and FEC strategy - and shape long-term roadmap toward 1.6T and 3.2T link aggregates. Customer & Standards Engagement: Lead technical engagement with hyperscale, AI accelerator, and optical module customers; represent the company in OIF CEI, IEEE 802.3, and related standards activities. End-to-End Link Modeling: Build and maintain MATLAB/Python models of the full link across electrical and optical media: channel response (backplane, copper cable, chip-to-chip, fiber), TX/RX impairments, jitter (RJ/DJ/BUJ), crosstalk, reflections, optical impairments (CD, PMD, laser phase noise, optical SNR), ADC/DAC quantization, and FEC performance under realistic BER/FLR targets. DSP Algorithm Architecture: Own the DSP pipeline across electrical and optical paths - FFE, DFE, MLSE/MLSD, CTLE-DSP partitioning, adaptive equalization (LMS, sign-sign LMS, blind adaptation), timing recovery and CDR, baseline wander correction, IQ/skew calibration, PAM demapping, and integration with KP4 / concatenated / soft-decision FEC. For optical links, additionally drive chromatic dispersion (CD) compensation, polarization demultiplexing, carrier phase and frequency recovery, and nonlinear compensation. Mixed-Signal Co-Design: Drive ADC/DAC architectural decisions - sample rate, resolution (ENOB), time-interleaving, calibration strategy - and align analog front-end, CTLE, and clocking specs with DSP performance budgets. Fixed-Point & Implementation Trade-offs: Drive wordlength optimization, parallelism and pipelining strategies for multi-hundred-GSps datapaths, and float-to-fixed methodology to balance BER performance, area, and pJ/bit power efficiency. Specifications & Cross-Domain Integration: Generate block-level specs for DSP datapaths, FEC, calibration, ADC/DAC, AFE, and clocking; align decisions across digital, mixed-signal, packaging, and SI/PI domains. DSP-to-RTL Handoff: Translate DSP reference models into hardware-friendly architectures with bit-true/cycle-accurate alignment, and partner with RTL and verification teams on micro-architecture, latency, and memory trade-offs. Silicon Bring-up & Validation: Partner with validation and lab teams to correlate post-silicon BER, eye, and link-training results with modeled assumptions; define KPIs (BER, FLR, link margin, power, latency) and debug methodologies. Mentorship & Thought Leadership: Guide DSP, systems, and hardware engineers; develop reusable models and best practices; contribute to architecture reviews, IP innovation strategy, and customer-facing technical engagements. ## Related Videos - [The Gashlycrumb Tinies of AI Networking You Must Know (or Languish!)](https://www.wearedevelopers.com/videos/2067-the-gashlycrumb-tinies-of-ai-networking-you-must-know-or-languish) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) - [Leveraging Large Language Models for Legacy Code Translation: Challenges and Solutions](https://www.wearedevelopers.com/videos/1157-leveraging-large-language-models-for-legacy-code-translation-challenges-and-solutions) - [Building a hypercar from scratch](https://www.wearedevelopers.com/videos/607-building-a-hypercar-from-scratch) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Docker network without Docker](https://www.wearedevelopers.com/videos/1418-docker-network-without-docker) ## Related Articles - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [Why Event-Driven Architecture Isn’t About Speed (and When You Actually Need It)](https://www.wearedevelopers.com/magazine/745-why-event-driven-architecture-isn-t-about-speed-and-when-you-actually-need-it) - [Highest Paying Tech Companies for Developers](https://www.wearedevelopers.com/magazine/220-highest-paying-tech-companies-for-developers) - [Best US AI Conferences for CTOs in 2026: Build vs. Buy, Vendor Evaluation, and Peer Intelligence](https://www.wearedevelopers.com/magazine/736-best-us-ai-conferences-for-ctos-in-2026-build-vs-buy-vendor-evaluation-and-peer-intelligence) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers)