> Markdown version of [/jobs/ext/2708948-applications-engineer](https://www.wearedevelopers.com/jobs/ext/2708948-applications-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Applications Engineer - **Company:** Efficient LLC - **Location:** United States - **Experience:** Expert - **Salary:** $160,000.0 - $210,000.0 - **Contract:** Permanent contract - **Skills:** Computer Engineering, Software Debugging, Formal Verification, Python (Programming Language), Regression Analysis, Static Timing Analysis, SystemVerilog, Tcl (Programming Language), Linux Virtual Server, Network Switches, Application Specific Integrated Circuits, Information Technology, Epic ECSM, Physical Design - **Published:** September 4, 2026 - **Apply:** https://startup.jobs/applications-engineer-silicon-ip-efficient-computer-9784166 ## About the Role * BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field. * 5+ years of experience in ASIC/SoC verification, physical design, silicon IP integration, or a closely related applications engineering role. * Strong scripting and automation skills-Python, TCL, Make, or shell-for building flows, regressions, and debug tooling. * Hands-on experience integrating third-party or internally licensed silicon IP, such as soft or hard macros, protocol or interface IP, interconnect, standard-cell libraries, or memory compilers. * Experience diagnosing complex integration issues and translating deep technical findings into clear, actionable guidance for customers and internal teams. * Familiarity with multiple foundries or process nodes and the verification, PPA, reliability, and signoff challenges associated with them. * One or more of the following experience areas: * Strong SystemVerilog/UVM skills, comfort reading and debugging RTL, and experience with coverage-driven verification using simulators such as Xcelium, VCS, or Questa. * Practical experience with synthesis, floorplanning, place-and-route, and static timing analysis using tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, or Tempus. * Working knowledge of timing models and physical abstracts (Liberty/ECSM/CCS and LEF), constraints and low-power intent (SDC and UPF), and signoff flows (STA, IR/EM, DRC/LVS). Willingness to travel to customer sites approximately 20-30%, depending on business needs. Nice to Have * Experience as an IP vendor applications engineer, verification or physical-design consultant, or silicon IP integrator at a systems/SoC company. * Experience with formal verification, protocol compliance suites, verification IP, low-power design, SoC-level DFT, or reliability signoff. * Experience with processor-based SoC integration, cache-coherent fabrics, and high-speed chip-to-chip or peripheral interfaces relevant to Efficient's platform. * Public speaking, technical training, or conference presentation experience ## Description We're looking for an Applications Engineer who will help customers successfully evaluate, integrate, verify, and physically implement our silicon IP in their SoCs. You'll be the technical bridge between customers and our design, verification, physical design, and characterization teams-helping customers stand up verification environments, close coverage and timing, resolve integration issues, and keep tapeouts on schedule. This customer-facing role combines broad ASIC/SoC expertise, hands-on problem solving, and clear technical communication., * Serve as the primary technical point of contact for customers integrating our silicon IP, from RTL simulation and UVM testbench setup through synthesis, floorplanning, place-and-route, timing closure, and signoff. * Debug customer-reported issues across the RTL, testbench, constraints, and physical implementation boundary; distinguish IP defects and deliverable issues from configuration errors, protocol misunderstandings, constraints, or implementation choices. * Develop and maintain reference verification environments, example testbenches, implementation flows, floorplan guidance, and integration collateral-including SDC and UPF templates-that reduce customer ramp time. * Deliver onsite and remote technical training on IP architecture, verification methodology, verification IP usage, coverage closure, timing models, physical abstracts, and implementation best practices. * Partner with engineering and product leaders to aggregate field evidence, prioritize corrective work, and shape future capabilities, deliverables, and release content. * Support pre-sales technical evaluations by helping prospective customers assess IP quality, verification collateral, PPA, floorplan compatibility, node/process readiness, and integration effort. * Lead architecture-to-signoff reviews of customer integrations, identify implementation risks, and recommend corrective actions across configuration, verification, performance, timing, power, and area. * Exercise upcoming IP releases and customer collateral in representative integration flows; document gaps and work with engineering owners to close them before external delivery. * Advise customers on interface and protocol integration, multi-voltage and power-domain design, DFT stitching at the IP boundary, and node-specific signoff requirements. * Turn recurring support cases into reusable enablement-including reference examples, diagnostic playbooks, automation, and self-service guidance-that shortens resolution time for customers and the field team. * Track and report field issues and recurring integration patterns to inform the IP roadmap, deliverable quality, and process-node support priorities. ## Related Videos - [Building a fully automated escape room](https://www.wearedevelopers.com/videos/735-building-a-fully-automated-escape-room) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Designing for Every Direction: Logical CSS for Global, Adaptive, and Effortlessly Reversible UIs](https://www.wearedevelopers.com/videos/2026-designing-for-every-direction-logical-css-for-global-adaptive-and-effortlessly-reversible-uis) - [You don't need to write the code. You need to become a verification architect and prove it's correct](https://www.wearedevelopers.com/videos/100023-you-don-t-need-to-write-the-code-you-need-to-become-a-verification-architect-and-prove-it-s-correct) - [The Neuro-Architecture of Productivity: How Work Environments Impact Cognitive Performance](https://www.wearedevelopers.com/videos/1122-the-neuro-architecture-of-productivity-how-work-environments-impact-cognitive-performance) ## Related Articles - [What is Software Engineering?](https://www.wearedevelopers.com/magazine/289-what-is-software-engineering) - [Where To Find Software Engineering Jobs](https://www.wearedevelopers.com/magazine/396-where-to-find-software-engineering-jobs) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Software Engineer Career: Things You Should Know](https://www.wearedevelopers.com/magazine/143-software-engineer-career-things-you-should-know) - [Where to Find Entry-Level Software Engineering Jobs](https://www.wearedevelopers.com/magazine/397-where-to-find-entry-level-software-engineering-jobs) - [Is Software Engineering Hard?](https://www.wearedevelopers.com/magazine/448-is-software-engineering-hard)