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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Digital Verification Engineer - **Company:** NEXTHOP SYSTEMS INC. - **Location:** Santa Clara, CA, United States - **Experience:** Experienced - **Contract:** Permanent contract - **Skills:** Test Suite, Code Coverage, Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Firmware, Field-Programmable Gate Array (FPGA), Hardware Design, SystemVerilog, Verilog, Application Specific Integrated Circuits, ModelSim - **Published:** September 4, 2026 - **Apply:** https://startup.jobs/digital-verification-engineer-nexthop-systems-inc-8784485 ## About the Role * Experience: 3-7 years of digital verification experience on FPGA or ASIC designs. * Language: Proficiency in Verilog (SystemVerilog strongly preferred). * Tools: Hands-on experience with logic simulators - Modelsim / Questasim and/or NC-Verilog. * Methodology: Solid grounding in logic-simulation and verification fundamentals - testbench construction, constrained-random stimulus, functional / code coverage, and assertions. * Education: BS/MS in Electrical Engineering, Computer Engineering, or a related field. Strong Pluses * Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols). * Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation. * Structured verification methodology experience (UVM or equivalent). * Familiarity with networking / switching datapaths or high-speed interfaces. ## Description 1. Verification Environment Ownership * Own the testbench: Design, build, and maintain the verification environments for our digital subsystems - from block level through full-chip / subsystem integration - for both FPGA and ASIC targets. * Reusable methodology: Establish and evolve reusable verification components (drivers, monitors, scoreboards, checkers) so new blocks plug into a consistent, maintainable framework instead of one-off testbenches. * Reference modeling: Develop behavioral / reference models where needed to independently predict expected DUT behavior and catch discrepancies automatically. 2. Test Development & Coverage * Test suites: Author directed and constrained-random tests that exercise functional modes, corner cases, error injection, and reset / clock-domain behavior. * Coverage-driven closure: Define functional and code-coverage goals and drive them to closure - identifying coverage holes and writing the stimulus to fill them. * Assertions: Embed assertions (SVA) to catch protocol and interface violations at the source, close to where they occur. 3. Simulation, Debug & Regression * Logic simulation: Run and debug simulations using Modelsim / Questasim and NC-Verilog; triage failures to root cause and partner with RTL designers on the fix. * Regression: Stand up and maintain automated regression suites - keeping them fast, deterministic, and green so the team gets rapid feedback on every RTL change. * Waveform debug: Debug efficiently at the waveform level and produce clear, reproducible failure reports that shorten the design-debug loop. 4. System Bring-up & HW/SW Co-validation * Bring-up support: Support lab bring-up of FPGAs and boards, correlating pre-silicon simulation behavior against real hardware. * Software collaboration: Partner with firmware / software engineers during system bring-up - validating register maps, interfaces, and boot / init sequences across the HW/SW boundary. * Milestone sign-off: Contribute to verification exit criteria for design milestones, documenting coverage and open issues so the team can make informed tape-out / release decisions. ## Related Videos - [Playing Pong on a shoulder press machine](https://www.wearedevelopers.com/videos/100140-playing-pong-on-a-shoulder-press-machine) - [When testing just doesn’t cut it](https://www.wearedevelopers.com/videos/720-when-testing-just-doesn-t-cut-it) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Agent Smith Gets Hardware: Autonomous IoT Hacking From Debug Port to Cloud API](https://www.wearedevelopers.com/videos/100258-agent-smith-gets-hardware-autonomous-iot-hacking-from-debug-port-to-cloud-api) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [When Agents Meet Legacy: Never Change a Running System](https://www.wearedevelopers.com/videos/100320-when-agents-meet-legacy-never-change-a-running-system) ## Related Articles - [9 Ways to Make Money Hacking](https://www.wearedevelopers.com/magazine/333-9-ways-to-make-money-hacking) - [What is Software Engineering?](https://www.wearedevelopers.com/magazine/289-what-is-software-engineering) - [Top 6 Hackathons for Developers in 2023](https://www.wearedevelopers.com/magazine/263-top-6-hackathons-for-developers-in-2023) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Software Engineer Career: Things You Should Know](https://www.wearedevelopers.com/magazine/143-software-engineer-career-things-you-should-know) - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again)