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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Design for Test (DFT) Engineer - **Company:** Positron Ai, Inc. - **Location:** United States (Remote available) - **Salary:** $200,000.0 - $350,000.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Code Coverage, Computer Engineering, Software Debugging, Microprocessors, Perl (Programming Language), Emulators, Event Logging, Firmware, Field-Programmable Gate Array (FPGA), Python (Programming Language), Key Management, PCI Express, System Software, SystemVerilog, Systems Integration, Tcl (Programming Language), Verilog, Scripting, Graphics Processing Unit (GPU), Application Specific Integrated Circuits, Backend, Physical Design - **Published:** September 4, 2026 - **Apply:** https://startup.jobs/design-for-test-dft-engineer-principal-current-45-8728078 ## About the Role * BS, MS, or PhD in Electrical Engineering or Computer Engineering * 12+ years of ASIC development experience * Extensive hands-on DFT implementation experience on complex SoCs, with multiple successful production tapeouts * Strong understanding of scan architectures, ATPG, memory BIST, logic BIST, boundary scan, IJTAG, test compression, fault models, and structural coverage analysis * Experience with leading DFT tool suites (e.g., Siemens Tessent, Synopsys TestMAX DFT, Cadence Modus, or equivalent) * Strong RTL skills using Verilog/SystemVerilog * Experience with synthesis and gate-level verification * Strong scripting skills (Python, Tcl, Perl, or similar) * Excellent debugging skills across RTL, netlists, and silicon test * Demonstrated ability to drive technical execution across cross-functional engineering teams Preferred Qualifications * Experience with high-performance AI accelerators, GPUs, CPUs, networking ASICs, PCIe, HBM, LPDDR, or chiplet architectures * High-speed SerDes and advanced process nodes (5nm and below) * Low-power design, yield enhancement methodologies, and manufacturing test optimization * Silicon bring-up, failure analysis, and post-silicon debug * Secure manufacturing and DFT: understanding of the interaction between secure boot, hardware root of trust, scan access control, fuse programming, key management, and production test * In-system debug and observability: experience architecting debug infrastructure (trace, event logging, test registers, scan visibility) that accelerates emulation and first-silicon bring-up * Emulation and pre-silicon validation: familiarity with Palladium/ZeBu/Veloce or FPGA prototyping to validate DFT features before tapeout * Third-party IP integration: experience auditing, integrating, and validating DFT collateral from multiple IP vendors to ensure a coherent full-chip DFT architecture, not just block-level stitching ## Description Positron AI is building next-generation AI inference accelerators, starting with our first ASIC, Asimov, with additional generations already underway. As Principal DFT Engineer, you'll own DFT and DFx strategy end-to-end: defining the DFT architecture for our accelerators, integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation. This is a hands-on, technical ownership role spanning architecture through tapeout and into first silicon, not a coordination role., Own the Positron DFT strategy * Define and maintain the DFT architecture for Asimov and future ASIC generations. * Develop long-term DFT and DFx roadmaps aligned with product quality, manufacturing, yield, diagnostics, and reliability objectives. * Establish DFT design standards, review processes, signoff criteria, and best practices across the engineering organization. Hands-on DFT implementation * Architect and implement scan insertion, compression, ATPG, memory BIST, logic BIST (where appropriate), boundary scan / IEEE 1149.x, IJTAG / IEEE 1687 infrastructure, and debug/observability features. * Integrate DFT into internally developed RTL. * Evaluate and integrate DFT capabilities from third-party IP providers. * Work directly in RTL, synthesis, and DFT tool flows. Drive pre-silicon DFT verification * Develop comprehensive DFT verification plans. * Validate DFT functionality through simulation and gate-level verification. * Ensure structural coverage targets are achieved before tapeout. * Drive DDA, stuck-at, transition, cell-aware, and power-aware ATPG strategies. * Own DFT signoff. Partner with Physical Design * Work closely with backend implementation teams to ensure successful physical realization of DFT architecture. * Guide scan chain partitioning, compression planning, and test clock architecture. * Address power-aware test implementation, timing closure considerations, and test mode integration. Own external DFT execution * Serve as Positron's technical lead for all DFT work performed by external design services partners. * Review implementation quality and conduct design reviews. * Drive issue resolution. * Define deliverables and acceptance criteria. * Ensure external work meets Positron quality standards. Cross-functional leadership * Partner closely with RTL designers, design verification, physical design, package and test engineering, firmware, system software, and silicon validation to ensure DFT is designed in from architecture through silicon bring-up. AI-enabled engineering * Leverage modern AI tools to improve engineering productivity, including automated review of DFT reports, ATPG analysis, coverage analysis, regression triage, documentation generation, workflow automation, and agentic engineering assistants. * Continuously evaluate new AI techniques that accelerate DFT development while improving quality. ## Related Videos - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Developing the Backend with Stefan Lingler, CTO at Shpock](https://www.wearedevelopers.com/videos/100360-developing-the-backend-with-stefan-lingler-cto-at-shpock) - [Playing Pong on a shoulder press machine](https://www.wearedevelopers.com/videos/100140-playing-pong-on-a-shoulder-press-machine) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Nest.js - TypeScript in the backend can also be clean](https://www.wearedevelopers.com/videos/1033-nest-js-typescript-in-the-backend-can-also-be-clean) - [Agent Smith Gets Hardware: Autonomous IoT Hacking From Debug Port to Cloud API](https://www.wearedevelopers.com/videos/100258-agent-smith-gets-hardware-autonomous-iot-hacking-from-debug-port-to-cloud-api) ## Related Articles - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [The 8 Best Code Testing Tools](https://www.wearedevelopers.com/magazine/402-the-8-best-code-testing-tools) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers) - [Dev Digest 132 - Binging WADFlix?](https://www.wearedevelopers.com/magazine/473-dev-digest-132-binging-wadflix)