> Markdown version of [/jobs/ext/2710214-rtl-designer-interconnect-noc-design](https://www.wearedevelopers.com/jobs/ext/2710214-rtl-designer-interconnect-noc-design). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # RTL Designer - Interconnect/NoC Design - **Company:** Moore's Law - **Location:** San Jose, CA, United States (Remote available) - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Computer Engineering, Hardware Security Module, Static Timing Analysis, Data Streaming, SystemVerilog, Integration Tests, Physical Design - **Published:** September 4, 2026 - **Apply:** https://startup.jobs/senior-rtl-designer-interconnect-noc-design-tylsemi-8759190 ## About the Role If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits., * BS/MS in Electrical Engineering, Computer Engineering, or equivalent with 8+ years of digital IC design, with at least 4 years owning on-chip interconnect, bus fabric, or NoC architecture at block-lead or integration-lead level. * Deep expertise in one or more on-chip interconnect protocols: AXI4 / AXI4-Lite / AXI-Stream; CHI or equivalent; able to write and review bus bridge RTL and understand ordering rules, response channels, and error signaling. * Experience with Network-on-Chip (NoC) design or integration of commercial NoC IP (in a complex SoC). * Familiarity with AMBA CHI or ACE coherency extensions and their impact on fabric design. * Solid understanding of CDC design: async FIFO design, gray-code counters, synchronizer topologies, and CDC verification methodology. * Experience owning the top-level integration netlist or chip-level assembly RTL on a multi-block design. * Strong SystemVerilog skills: arbiters, FIFOs, pipelines, address decoders, and parameterized bus infrastructure. * Experience with static timing constraints for multi-clock designs Good To Have * Background with high-speed chiplet or SoC integration at advanced nodes (7 nm or below), including floorplan-driven bus topology decisions. * Experience building or maintaining an automated register-map generation flow (SystemRDL, IP-XACT, or similar). * Prior role as chip-level integration lead responsible for assembling subsystem IPs into a complete design. * Familiarity with hardware security primitives: access control, firewall IP, or trusted execution region isolation in the fabric. * Experience with formal property verification of bus protocols or CDC crossings. ## Description * No endless meetings, no PowerPoint presentations to convince middle management., * Define on-chip fabric topologies connecting the multiple subsystems * Specify the data-path fabric for the high-bandwidth routes: bandwidth provisioning, pipeline depth, buffering strategy, and back-pressure propagation between major subsystems. * Architect the register-access fabric with address decoding and access-protection logic. * Define the arbitration and QoS policy for shared fabric resources: priority assignment per traffic class, bandwidth reservation, and starvation-prevention mechanisms. * Own the fabric error-handling architecture: how illegal accesses, timeouts, and protocol violations are detected, logged, and reported to the management subsystem. * Own the CDC strategy for every clock-domain boundary on the die - and documenting the timing constraints for each. * Own or closely review all fabric RTL: bus bridges, async FIFOs, arbiters, address decoders, and pipeline registers that form the on-chip interconnect. * Drive integration assembly: own the top-level connectivity netlist that instantiates all major blocks and wires them through the fabric, serving as the integration point of truth. * Coordinate with subsystem leads align on interface protocols, handshake semantics, and reset sequencing at each fabric boundary. * Define and own the fabric performance model: estimate bandwidth utilization per path under representative traffic mixes for each operating mode and identify bottlenecks. * Establish fabric-level bring-up tests: register accessibility checks, path connectivity tests, and loopback sequences that confirm the interconnect is healthy before full subsystem integration testing begins. * Coordinate with the physical design team on fabric floorplan implications: block placement driven by dominant data flow, clock-region boundaries, and wire-length budgets for timing closure. ## Related Videos - [Python-Based Data Streaming Pipelines Within Minutes](https://www.wearedevelopers.com/videos/1233-python-based-data-streaming-pipelines-within-minutes) - [Building a fully automated escape room](https://www.wearedevelopers.com/videos/735-building-a-fully-automated-escape-room) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Designing for Every Direction: Logical CSS for Global, Adaptive, and Effortlessly Reversible UIs](https://www.wearedevelopers.com/videos/2026-designing-for-every-direction-logical-css-for-global-adaptive-and-effortlessly-reversible-uis) - [Building a hypercar from scratch](https://www.wearedevelopers.com/videos/607-building-a-hypercar-from-scratch) - [Why and when should we consider Stream Processing frameworks in our solutions](https://www.wearedevelopers.com/videos/1085-why-and-when-should-we-consider-stream-processing-frameworks-in-our-solutions) ## Related Articles - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [Are design and development really just the same thing?](https://www.wearedevelopers.com/magazine/520-are-design-and-development-really-just-the-same-thing) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers) - [Events like RSAC Get You CISOs. Developers Decide What Actually Gets Deployed.](https://www.wearedevelopers.com/magazine/693-events-like-rsac-get-you-cisos-developers-decide-what-actually-gets-deployed)