> Markdown version of [/jobs/ext/2712513-design-for-test-engineer](https://www.wearedevelopers.com/jobs/ext/2712513-design-for-test-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Design for Test Engineer - **Company:** Apple Inc. - **Location:** Cupertino, CA, United States - **Experience:** Experienced - **Salary:** $146,717.0 - $218,000.0 - **Contract:** Permanent contract - **Skills:** Computer Engineering, Software Debugging, Perl (Programming Language), Joint Test Action (IEEE Standards), Python (Programming Language), Static Timing Analysis, Verilog - **Published:** September 4, 2026 - **Apply:** https://www.techcareers.com/job.asp?id=3377298809&tx=KK9393FFU&pt=1&aff=0B19D771-A501-4A5E-8338-2A822B784D54&utm_source=Job%20Feed&utm_medium=textkernel&utm_campaign=DE&utm_term=0B19D771-A501-4A5E-8338-2A822B784D54 ## About the Role * Master's degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field and 2 years of experience in the job offered or related occupation. * Experience and/or education must include: * Designing and verifying RTL using Verilog hardware description language. * Knowledge of MBIST, march algorithms and memory fault models. * Designing Joint Test Action Group (JTAG) architecture and programming DFT control registers for chip testing * Automating DFT design flows using Python or Perl scripting languages * Knowledge of STA for timing analysis. * Running RTL and gate-level simulations using industry-standard tools such as VCS or NCSIM to debug and resolve design issues * Utilizing Automatic Test Pattern Generation (ATPG) tools for scan pattern generation and fault coverage analysis across various fault models * Performing silicon failure diagnosis and analysis from Automated Test Equipment (ATE) to improve yield and manufacturing processes * Applying low-power design techniques to reduce overall chip power consumption ## Related Videos - [Breaking the Bug Cycle: TDD for the Win](https://www.wearedevelopers.com/videos/1037-breaking-the-bug-cycle-tdd-for-the-win) - [Swapping a Data Warehouse at Runtime: Zero-Downtime Migration Without Changing a Single Client](https://www.wearedevelopers.com/videos/100311-swapping-a-data-warehouse-at-runtime-zero-downtime-migration-without-changing-a-single-client) - [Using AI Without Losing Your Skills](https://www.wearedevelopers.com/videos/2045-using-ai-without-losing-your-skills) - [Building the Right Product and Building It Right: A Glimpse into Extreme Programming, Atomic Design ](https://www.wearedevelopers.com/videos/398-building-the-right-product-and-building-it-right-a-glimpse-into-extreme-programming-atomic-design) - [Agentic AI: building autonomous systems for developers](https://www.wearedevelopers.com/videos/100034-agentic-ai-building-autonomous-systems-for-developers) - [What I learned as a developer from accidents in space](https://www.wearedevelopers.com/videos/642-what-i-learned-as-a-developer-from-accidents-in-space) ## Related Articles - [The 8 Best Code Testing Tools](https://www.wearedevelopers.com/magazine/402-the-8-best-code-testing-tools) - [Should senior developers refuse interview coding challenges?](https://www.wearedevelopers.com/magazine/29-should-senior-developers-refuse-interview-coding-challenges) - [What is a Test Plan: Guide to Test Planning](https://www.wearedevelopers.com/magazine/191-what-is-a-test-plan-guide-to-test-planning) - [Software Engineer Career: Things You Should Know](https://www.wearedevelopers.com/magazine/143-software-engineer-career-things-you-should-know) - [How to create a test plan for software testing](https://www.wearedevelopers.com/magazine/56-how-to-create-a-test-plan-for-software-testing) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers)