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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Staff Power Performance Architect - **Company:** d Matrix - **Location:** Santa Clara, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Computer-Aided Design, Application Programming Interfaces (APIs), Artificial Intelligence, Computer Programming, Computer Engineering, System Configuration, Microarchitecture, Software Debugging, Digital Technology, Python (Programming Language), Software Requirements Analysis, Tcl (Programming Language), Backend, Information Technology, Performance Monitor, Front End Software Development, Physical Design - **Published:** September 4, 2026 - **Apply:** https://startup.jobs/sr-staff-power-performance-architect-d-matrix-8301669 ## About the Role * 8+ years of relevant experience in IC power/performance architecture, RTL, or physical design, with a Master's degree in Electrical Engineering, Computer Engineering, or Computer Science. * Solid understanding of power, performance, micro-architecture, RTL, and physical design in the context of digital system and IC design, including the full IC design flow (Arch * uarch * RTL * Schematic * Layout * Verification * Fabrication * HVM). * Familiarity with at least one EDA tool for power estimation. * Ability to move fluidly between RTL, physical design, and automation, including building script utilities to improve design execution productivity across the design team. * Programming proficiency in TCL and Python, with experience using libraries, APIs, data parsing, and algorithmic thinking. * Self-motivated with a fast, iterative approach to design work, sound engineering judgment, and a bias toward action., * Exposure to power estimation and performance metrics such as TDP, PMAX, EDP, Peak, and Average. * Familiarity with power/frequency scaling techniques (DFS, DVFS, AFS, AVFS). * Familiarity with power delivery network (PDN) analysis, including resonance, impedance (Z(f)), and voltage droop analysis. ## Description d-Matrix is looking for a Senior Staff Power Performance Architect to own pre-silicon power estimation across our next-generation AI accelerators. In this role, you will drive both RTL-level and physical-design-level power estimation, and build an architectural power estimation tool that models power from system configuration and die-level metrics for AI workloads. You will partner closely with front-end architects, DV engineers, and backend design teams to identify power activity windows, define performance monitoring requirements, and translate that analysis into hardware capability improvements and die-level design changes. This role also contributes directly to micro-architecture and RTL design, verification, and silicon bring-up, making it central to how d-Matrix balances performance and power efficiency at the silicon level., * Own pre-silicon power estimation for design blocks, spanning both RTL-level and physical-design-level estimation. * Partner with front-end and DV engineers to identify power activity windows, and work with the RTL team to implement estimation feedback and optimize power. * Build an architectural power estimation tool for AI workloads that computes power from system configuration and die-level metrics, including workload profiling based on memory size, bandwidth, and gate counts of compute/memory blocks. * Collaborate with frontend architects and backend design to define performance monitor availability, system requirements, and usage, then drive that analysis into hardware capability improvements and die-level design modifications. * Lead micro-architecture and RTL design, synthesis, and logic/physical power-performance verification using leading-edge CAD tools and semiconductor process technologies. * Design and implement performance-enabling and power-saving/monitoring functions that support efficient design, test, and debug, and participate in silicon bring-up and validation. ## Related Videos - [Move fast with Software Architecture](https://www.wearedevelopers.com/videos/206-move-fast-with-software-architecture) - [Developing the Backend with Stefan Lingler, CTO at Shpock](https://www.wearedevelopers.com/videos/100360-developing-the-backend-with-stefan-lingler-cto-at-shpock) - [Building a fully automated escape room](https://www.wearedevelopers.com/videos/735-building-a-fully-automated-escape-room) - [Engineering/Manager Pendulum: Generating compound interest on your career](https://www.wearedevelopers.com/videos/100348-engineering-manager-pendulum-generating-compound-interest-on-your-career) - [Nest.js - TypeScript in the backend can also be clean](https://www.wearedevelopers.com/videos/1033-nest-js-typescript-in-the-backend-can-also-be-clean) - [Designing for Every Direction: Logical CSS for Global, Adaptive, and Effortlessly Reversible UIs](https://www.wearedevelopers.com/videos/2026-designing-for-every-direction-logical-css-for-global-adaptive-and-effortlessly-reversible-uis) ## Related Articles - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Data Science & more: The Lopez dilemma](https://www.wearedevelopers.com/magazine/10-data-science-more-the-lopez-dilemma) - [From developer to manager – what does it take to become an engineering manager?](https://www.wearedevelopers.com/magazine/42-from-developer-to-manager-what-does-it-take-to-become-an-engineering-manager) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers) - [Top Characteristics of a Software Engineer](https://www.wearedevelopers.com/magazine/166-top-characteristics-of-a-software-engineer)