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# Sr. SoC Power & Performance Architect, AI Hardware in , United States

- **Company:** Energy Jobline
- **Location:** Palo Alto, CA, United States
- **Experience:** Expert
- **Salary:** $160,000.0 - $312,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Computer Engineering, Software Architecture, Information Technology, Optimization Algorithms, Hardware Acceleration
- **Published:** September 4, 2026
- **Apply:** https://www.energyjobline.com/job/sr-soc-power-performance-architect-ai-hardware-united-states-31472172

## About the Role

Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field or equivalent practical experience
Experience with power management, low-power architecture, and power optimization techniques (multi-Vth/power/voltage-domain design, clock gating, power gating, DVFS, AVS)
Knowledge of energy-efficient chip design fundamentals and related tradeoffs
Understanding of processors (GPU a plus), system-software architectures, and their performance/power modeling techniques
Familiarity with performance monitors and simulators used in modern processor architectures
Experience across the full product-delivery cycle (definition, architecture, design and implementation, testing, and productization)
Strong grasp of performance/power estimation and optimization methodology
Minimum 5 years of industry experience related to power/performance estimation and optimization (senior-level candidates with 10+ years in power management or low-power design/methodology strongly )

## Description

Lead the definition of power requirements for AI accelerator SoCs to optimize Power-Performance-Area (PPA) under peak current and thermal constraints
Own and drive cross-functional teams to deliver on competitive power key performance indicators (KPIs) for one or more major SoC IPs such as the compute fabric, memory subsystem, or multimedia subsystem
Propose and drive power and performance optimizations throughout the design process, from concept to mass productization
Apply low-power design techniques including multi-VT, clock gating, power gating, and Dynamic Voltage-Frequency Scaling (DVFS/AVS)
Drive power-performance trade-off analysis to inform engineering reviews and product roadmap decisions
Develop and refine power and performance models for processors and system-software architectures
Partner with cross-functional teams (architecture, RTL design, implementation, verification, and performance engineering) throughout the design flow
Represent the status of SoC power to the executive leadership team


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