> Markdown version of [/jobs/ext/2716816-emulation-test-engineer](https://www.wearedevelopers.com/jobs/ext/2716816-emulation-test-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md).

---

# Emulation Test Engineer

- **Company:** Positron Ai, Inc.
- **Location:** United States (Remote available)
- **Experience:** Expert
- **Salary:** $180,000.0 - $300,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Bash Shell, Computer Engineering, Data Centers, Software Debugging, Emulators, Ethernet, Firmware, Python (Programming Language), PCI Express, Software Engineering, SystemVerilog, Tcl (Programming Language), Verilog, Application Specific Integrated Circuits, Information Technology, Power Analysis (Cryptography)
- **Published:** September 4, 2026
- **Apply:** https://startup.jobs/emulation-test-engineer-current-45-8310995

## About the Role

* Deep Palladium Expertise: Extensive hands-on experience with Cadence Palladium (Z1/Z2/Z3), including advanced clocking, ICE (In-Circuit Emulation), and Virtual Interface (VIF) flows
 * Complex SoC Background: A track record of emulating multi-billion gate designs where partitioning, runtime predictability, and compile efficiency were critical success factors
 * Automation Mastery: Expert-level Python, Tcl, and Bash skills to build and maintain the infrastructure for automated model releases and nightly regressions
 * Hardware-Software Debug Skills: Proficiency in debugging low-level firmware and kernel-level issues using Verdi, SimVision, and hardware-software co-debug tools

Minimum Requirements

 * Education: BS/MS in Electrical Engineering, Computer Engineering, or Computer Science.
 * Experience: 8+ years in ASIC Emulation or Verification, with significant experience on large-scale Palladium installations
 * Technical Skills: Mastery of SystemVerilog, Verilog, and C/C++ for transactor development and reference modeling.
 * Protocol Knowledge: Deep understanding of data center protocols including PCIe, DDR and AMBA AXI/NoC

## Description

As Emulation Test Engineer, you'll provide technical direction for pre-silicon validation of Positron's next-generation AI inference ASIC. You'll own the end-to-end emulation strategy on the Cadence Palladium platform, architecting complex model builds, managing multi-rack partitioning, and driving the "left-shift" of our software development. You'll collaborate across RTL, DV, and Software teams to build high-performance virtual environments that prove out architectural functionality and accelerate firmware/OS bring-up months before tape-out. This role is critical to our silicon success: you'll set the emulation methodology, resolve hardware-software bottlenecks at scale, and ensure our design is silicon-ready.

What you'll do

 * Massive-Scale Model Architecture: Lead the partitioning and compilation of our design across a multi-rack Palladium environment, optimizing for performance and debug visibility.
 * Software Enablement (Left-Shift): Create and maintain the hybrid emulation and co-simulation environments (using SCE-MI or DPI) that allow our software teams to boot OS images and run AI workloads on pre-silicon hardware.
 * Full-Stack Validation: Design and execute comprehensive emulation test plans to verify high-speed interfaces (PCIe Gen 6/7, 112G+VSR, Ethernet) and complex AI memory hierarchies.
 * Performance & Power Analysis: Utilize Palladium's Dynamic Power Analysis (DPA) and throughput monitors to identify "true peaks" and performance bottlenecks that simulation cannot capture.
 * Vendor Management: Act as the primary technical point of contact with Cadence R&D to troubleshoot tool issues and leverage the latest Palladium Z3 capabilities.


## Related Videos

- [The Gashlycrumb Tinies of AI Networking You Must Know (or Languish!)](https://www.wearedevelopers.com/videos/2067-the-gashlycrumb-tinies-of-ai-networking-you-must-know-or-languish)
- [Playing Pong on a shoulder press machine](https://www.wearedevelopers.com/videos/100140-playing-pong-on-a-shoulder-press-machine)
- [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips)
- [Building a hypercar from scratch](https://www.wearedevelopers.com/videos/607-building-a-hypercar-from-scratch)
- [Docker network without Docker](https://www.wearedevelopers.com/videos/1418-docker-network-without-docker)
- [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right)

## Related Articles

- [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again)
- [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers)
- [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline)
- [Dev Digest 134 - Where pixels sing?](https://www.wearedevelopers.com/magazine/477-dev-digest-134-where-pixels-sing)
- [Dev Digest 137 - AI'm not sure about this](https://www.wearedevelopers.com/magazine/485-dev-digest-137-ai-m-not-sure-about-this)
- [Dev Digest 129 - Now that's what I call private data!](https://www.wearedevelopers.com/magazine/468-dev-digest-129-now-that-s-what-i-call-private-data)