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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # RTL Design Engineer - **Company:** Normal Computing - **Location:** United States - **Contract:** Permanent contract - **Skills:** Adobe InDesign, Artificial Intelligence, Microarchitecture, Software Debugging, Integrated Development Environments, Open Source Technology, Reduced Instruction Set Computing, System on a Chip, SystemVerilog, Application Specific Integrated Circuits, Formal Methods, Physical Design - **Published:** September 4, 2026 - **Apply:** https://startup.jobs/hardware-engineer-rtl-normal-computing-corporation-8697163 ## About the Role * Hands-on experience writing production RTL in SystemVerilog and closing it through synthesis and place-and-route * Experience in closing coverage to a high level * At least one tapeout in your background, from any node and any company size * Experience working on datapaths, pipelines, or custom logic where the microarchitecture was not fully specified upfront * Strong debugging instincts across simulation, waveforms, and formal counterexamples * Ability to work directly with architects and physical designers without needing a large intermediary layer * Industry experience in ASIC or SoC design Bonus Points * Experience at an AI chip company where design and verification were tightly coupled * Open-source RTL contributions to projects like Chipyard, OpenTitan, or CVA6 * Familiarity with RISC-V or other open ISAs * Experience with AI-assisted RTL or EDA tooling in your design workflow * Exposure to physical design constraints, floorplanning, or timing-driven RTL development ## Description As an RTL Design Engineer at Normal, you will design and verify the digital logic at the heart of Normal's thermodynamic hardware. This work sits at the intersection of classical ASIC design, novel computing architectures, and a development environment where the hardware and the algorithms are built together, not in sequence. You will own RTL from microarchitecture to tapeout: writing microarchitecture specifications, creating synthesizable SystemVerilog, working with design verification engineers fully test the design using conventional and formal methods, and working closely physical design to make sure the design meets area and timing constraints. Because Normal's chips are not standard accelerators, the RTL engineer here is closer to first-principles decisions than at a larger company. You will be shaping architecture, not just implementing it. This is a role for an engineer who collaborates effectively across teams, including architecture, verification and physical design. The strongest candidates have taped out silicon, written RTL and helped close coverage, and are comfortable working in an environment where the specification is still being developed in parallel., * RTL Design: Write and own synthesizable RTL in SystemVerilog across blocks ranging from datapath logic to control and memory interfaces. * Microarchitecture: Work with architecture to translate high-level specifications into implementable microarchitectures. * Verification: Work closely with the verification team to review verification plans, assist on debug, and become a partner in closing coverage. * Physical Design Collaboration: Collaborate with physical design on timing closure, floorplanning constraints, and DFT. * Design Reviews: Participate in design reviews and contribute to architecture decisions, not just implementation. * Tapeout & Bring-up: Support tapeout preparation, integration, and post-silicon bring-up as needed. ## Related Videos - [When testing just doesn’t cut it](https://www.wearedevelopers.com/videos/720-when-testing-just-doesn-t-cut-it) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [How to become an AI toolsmith](https://www.wearedevelopers.com/videos/653-how-to-become-an-ai-toolsmith) - [AI Meets Hoare Logic: Revolutionizing Software Testing with Formal Methods](https://www.wearedevelopers.com/videos/1644-ai-meets-hoare-logic-revolutionizing-software-testing-with-formal-methods) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [What’s New in Web? 2026 Edition](https://www.wearedevelopers.com/videos/100014-what-s-new-in-web-2026-edition) ## Related Articles - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Dev Digest 130 - The Diablo is in the details](https://www.wearedevelopers.com/magazine/470-dev-digest-130-the-diablo-is-in-the-details) - [Dev Digest 129 - Now that's what I call private data!](https://www.wearedevelopers.com/magazine/468-dev-digest-129-now-that-s-what-i-call-private-data)