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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Lead Hardware System Architect - **Company:** Bolt - **Location:** Sunnyvale, CA, United States (Remote available) - **Experience:** Expert - **Salary:** $200,000.0 - $250,000.0 - **Contract:** Permanent contract - **Skills:** Computer Engineering, Software Debugging, Electronic Design Automation, Hardware Design, OrCAD, PCI Express, Signal Integrity, Systems Architecture, Hardware Infrastructure, Pcb Layout, Physical Design - **Published:** September 4, 2026 - **Apply:** https://startup.jobs/lead-hardware-system-architect-bolt-graphics-9788578 ## About the Role * Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical discipline. * Experience: 8+ years of hardware design experience, with a proven track record of shipping high-performance graphics hardware, GPU motherboards, or high-density parallel compute accelerator boards. * Fabric & Bus Expertise: Deep, hands-on experience designing with PCIe Gen 5/6 and high-speed serdes (112G/224G PAM4 architectures). Familiarity with CXL or scalable interconnect fabrics is highly desired. * Advanced Power & SI/PI: Strong understanding of high-frequency PCB layout constraints, via optimization, and power delivery networks capable of handling extreme di/dt step loads inherent to dynamic graphics workloads. * Hardware Tooling: Proficiency with advanced EDA tools (e.g., Cadence Allegro, OrCAD) and familiarity with simulation tools for validating physical design assumptions. * Global Vendor Triage: Experience directing overseas ODM engineering teams through architectural definition, layout execution, and laboratory hardware triage., * Direct experience with Open Compute Project (OCP) standards or industry-standard multi-GPU form factors. * Familiarity with liquid cooling or advanced phase-change thermal infrastructure and its unique spatial and material constraints on physical board design. * Hands-on lab experience utilizing high-speed validation equipment (e.g., oscilloscopes, VNAs, BERTs) for signal and power verification on graphics hardware. ## Description As the Lead Hardware System Architect, you will own the end-to-end hardware development lifecycle for our next-generation graphics compute platforms, high-performance GPU servers, and ultra-high-speed PCIe graphics form factors. You will act as the technical bridge between advanced graphics silicon packaging and system-level deployment, driving physical architecture, functional partitioning, and high-speed fabric optimization for massive graphics workloads and real-time rendering infrastructure. In this role, you will not just oversee board layouts; you will define the physical topologies that enable cutting-edge graphics compute scaling. You will serve as the ultimate technical escalation point for our global JDM/ODM engineering partners, steering them through complex bring-up, signal integrity boundaries, and root-cause failure analysis to deliver flawless graphics hardware on schedule. This role is on-site, 5 days a week. What you'll do: 1. Physical System Architecture & High-Performance Graphics Design * Architect the Platform: Drive system-level architectural trade-offs, balancing high-performance GPU silicon package constraints, high-speed routing density, thermal mechanics, and ultra-high-density power delivery networks (PDNs). * Own High-Speed Topologies: Design and optimize complex PCB topologies utilizing PCIe Gen 5/Gen 6 (CEM specifications) and proprietary/consortium scale-up interconnect fabrics designed for parallel compute and graphics scaling (e.g., NVLink, Infinity Fabric, UA Link). * Systemic Co-Design: Collaborate with Silicon, Signal/Power Integrity (SI/PI), and Thermal/Mechanical teams to define robust board stack-ups, low-loss material selection, and multi-phase power zones handling massive transient loads from modern graphics processors. * Management Integration: Ensure seamless integration of out-of-band telemetry and management infrastructure, designing physical routing for Baseboard Management Controllers (BMCs), SPI, and I2C/SMBus topologies. 2. Technical JDM/ODM & Supplier Governance * Lead Technical Enablement: Serve as the primary technical authority interfacing with international JDM/ODM layout and hardware engineering teams. * Triage & Failure Analysis: Lead complex hardware debug, component-level troubleshooting, and failure analysis (FA) during early-phase platform bring-up and validation of graphics compute hardware. * DFX & Execution Governance: Enforce rigorous design reviews and strict compliance with DFX (Manufacturing, Assembly, Test, and Automation) standards to ensure high-yield transitions from EVT/DVT to High-Volume Manufacturing (HVM). ## Related Videos - [Breaking the Hardware Mindset: Overcoming Barriers to System-Level Innovation](https://www.wearedevelopers.com/videos/1635-breaking-the-hardware-mindset-overcoming-barriers-to-system-level-innovation) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Building a hypercar from scratch](https://www.wearedevelopers.com/videos/607-building-a-hypercar-from-scratch) ## Related Articles - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [The Best X (Twitter) Accounts for Developers](https://www.wearedevelopers.com/magazine/294-the-best-x-twitter-accounts-for-developers) - [Highest Paying Tech Companies for Developers](https://www.wearedevelopers.com/magazine/220-highest-paying-tech-companies-for-developers) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Dev Digest 129 - Now that's what I call private data!](https://www.wearedevelopers.com/magazine/468-dev-digest-129-now-that-s-what-i-call-private-data) - [Is Software Engineering Hard?](https://www.wearedevelopers.com/magazine/448-is-software-engineering-hard)