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# Digital Verification Engineer

- **Company:** Arago
- **Location:** Courbevoie, France
- **Contract:** Permanent contract
- **Skills:** Adobe InDesign, Boolean Algebra, Computer Engineering, Software Debugging, Formal Verification, Field-Programmable Gate Array (FPGA), PCI Express, Regression Testing, Reduced Instruction Set Computing, SystemVerilog, Application Specific Integrated Circuits
- **Published:** September 5, 2026
- **Apply:** https://startup.jobs/digital-verification-engineer-arago-8292720

## About the Role

* Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field.
 * Proven fluency and hands-on expertise in SystemVerilog for verification.
 * Demonstrated prior experience with the UVM framework and modern verification environments.
 * Direct knowledge of PCIe protocols and experience verifying digital logic for high-speed interfaces.
 * Practical experience verifying RISC-V CPU designs or equivalent digital processor architectures within an ASIC context.
 * Strong analytical and communication skills for customer-driven projects and interdisciplinary teamwork.
 * Language: English at a proficient level. French is a plus., * Proactive in anticipating and mitigating design risks, including the assessment of undetected flaws via coverage-driven and formal verification.
 * Proven ability to deliver in fast-paced, collaborative startup environments.
 * Ownership mindset, attention to detail, and commitment to high product quality.

## Description

* Develop robust verification plans for complex digital and mixed-signal optical chip designs.
 * Collaborate closely with architects, designers, and customers to understand logic requirements, translate them into verification strategies, and deliver clear, actionable feedback throughout the development process.
 * Perform netlist-level simulations with SDF back-annotation for timing-accurate verification
 * Support FPGA/ASIC bring-up and post-silicon validation as needed
 * Develop, maintain, and optimize testbenches and verification components using advanced SystemVerilog features, such as constrained random testing, assertions, and transaction-level modeling, to create robust coverage-driven environments.
 * Design scalable, reusable UVM-based environments and components (e.g., agents, monitors, scoreboards) for block- and system-level verification. Employ UVM to achieve regression automation, functional coverage closure, and high bug-detection efficiency.
 * Develop and execute verification strategies for digital blocks implementing or interfacing with PCI Express (PCIe). Apply protocol-checking, compliance validation, error injection, and debug skills for PCIe endpoints and root complex devices. Use protocol analyzers and simulation environments to validate correct implementation across all protocol layers.
 * Participate in the verification of RISC-V CPU cores and subsystems. Create test plans targeting processor modules (ALU, decoder, register file, control logic), with reference model comparisons, signature checks, and coverage of edge-case scenarios. Leverage formal verification and compliance suites for thorough design validation.
 * Plan and perform end-to-end ASIC verification, from block-level testbenches to full-chip integration. Execute functional and regression tests, formal verification, and coverage analysis. Debug and resolve design issues, ensuring pre-silicon reliability before manufacturing. Engage in design reviews and system-level protocol validation with cross-functional teams., * Technical meeting : Deep dive into your past projects and technical achievements.
 * CEO Interview : Assess the fit with the team's culture and long-term vision.
 * Reference Calls: Mandatory calls with your former managers to validate strengths, weaknesses, and work style.
 * Technical Assessment: Take-home technical assignment crafted to the role you're applying for.
 * Final Interview : Discuss your technical assignment and address any remaining questions with team members.


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