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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # FPGA Engineer - **Company:** University of Oxford - **Location:** UK - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Artificial Neural Networks, Boolean Algebra, C++ (Programming Language), Computer Engineering, Data Migration, Software Debugging, Logic Synthesis of Circuits, Digital Technology, Embedded Software, Ethernet, Field-Programmable Gate Array (FPGA), Hardware Description Language, High-Frequency Trading, Joint Test Action (IEEE Standards), Python (Programming Language), MATLAB, Machine Learning, PCI Express, Systems Architecture, System on a Chip, Tcl (Programming Language), Toolchain, VHSIC Hardware Description Language (VHDL), Vivado, Scripting, Application Specific Integrated Circuits, Optimization Algorithms, Bare Metal, Hardware Acceleration, Hardware Debugging - **Published:** September 5, 2026 - **Apply:** https://startup.jobs/fpga-engineer-quantum-dice-8247623 ## About the Role * Degree in Electrical Engineering, Computer Engineering, or a related field. * 5+ years of hands-on experience in FPGA digital design, including designing and debugging resource-intensive high-speed digital systems. * Expertise in HDL: Strong proficiency in HDL coding, and a proven track record of writing custom RTL from scratch. * PS/Embedded development knowledge: Practical understanding of processor-side development for FPGA SoC platforms, particularly Zynq or similar PS/PL architectures. Being comfortable writing or reviewing bare-metal C/C++ to configure PL peripherals through AXI registers, moving data between PS and PL. * Math to hardware: Proven ability to translate complex mathematical models into hardware accelerators, including bit-accurate system modelling and fixed-point arithmetic. * Digital design fundamentals: Solid understanding of advanced digital design concepts, including timing closure for highly utilised designs and clock domain crossing (CDC). * Toolchains: Deep experience with design and verification tools such as Xilinx Vivado, Vitis, and TCL scripting. * Lab/debug skills: Familiarity with hardware debugging tools, such as JTAG debuggers, oscilloscopes, spectrum analysers, signal generators, and logic analysers, and lab bring-up of custom boards. What makes you stand out * Synchronised FPGA interconnect network within a scalable cluster approach. * Demonstrated experience with implementing stochastic problems, optimisation algorithms, neural network, or artificial intelligence / machine learning algorithms into hardware. * Direct experience with the ASIC design flow: act as the critical bridge towards custom silicon by prototyping, emulating, and validating our probabilistic computing architectures on FPGA platforms prior to ASIC tape-out. * Experience designing highly optimised, low-latency computing architectures, such as high-frequency trading, custom digital signal processing, or high-performance computing ## Description * Algorithm implementation: Translate complex probabilistic algorithms from high-level models, such as pseudocode/Python/C++/MATLAB, into highly pipelined, resource-efficient FPGA RTL. * RTL design from scratch: Design and implement custom digital logic using VHDL where off-the-shelf vendor IPs are insufficient, bottlenecked, or introduce latency. * High-speed I/O integration: architect data acquisition pipelines interfacing with the analogue front end via ultra-fast ADCs and high-speed transceivers, as well as interfacing to high-throughput computer host architectures via PCIe and high-speed Ethernet. * System architecture: Work closely with hardware and software engineers, the research team, and ASIC architects to develop the high-level system architecture. * Verification & bring-up: Develop rigorous testbenches and simulations to ensure compliance with functional and timing requirements. Participate in lab bring-up and debugging of physical hardware. * Optimisation: Use advanced debugging tools and techniques to analyse and optimise performance, timing closure, power consumption, and resource utilisation across multiple clock domains. ## Related Videos - [The Gashlycrumb Tinies of AI Networking You Must Know (or Languish!)](https://www.wearedevelopers.com/videos/2067-the-gashlycrumb-tinies-of-ai-networking-you-must-know-or-languish) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Leveraging Large Language Models for Legacy Code Translation: Challenges and Solutions](https://www.wearedevelopers.com/videos/1157-leveraging-large-language-models-for-legacy-code-translation-challenges-and-solutions) - [Building a hypercar from scratch](https://www.wearedevelopers.com/videos/607-building-a-hypercar-from-scratch) - [Quantum Computing for Classical Developers](https://www.wearedevelopers.com/videos/1153-quantum-computing-for-classical-developers) - [Docker network without Docker](https://www.wearedevelopers.com/videos/1418-docker-network-without-docker) ## Related Articles - [Top 6 Hackathons for Developers in 2023](https://www.wearedevelopers.com/magazine/263-top-6-hackathons-for-developers-in-2023) - [Data Engineer Salary UK](https://www.wearedevelopers.com/magazine/253-data-engineer-salary-uk) - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [The Best X (Twitter) Accounts for Developers](https://www.wearedevelopers.com/magazine/294-the-best-x-twitter-accounts-for-developers) - [Why Upskilling And Reskilling is Important For Developers](https://www.wearedevelopers.com/magazine/428-why-upskilling-and-reskilling-is-important-for-developers) - [Software Engineer Salary London](https://www.wearedevelopers.com/magazine/252-software-engineer-salary-london)