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# ASIC Architect

- **Company:** ZP Group
- **Location:** New York, NY, United States
- **Experience:** Expert
- **Salary:** $270,000.0 - $290,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Computer Networks, Data Centers, Software Debugging, Microprocessors, Memory Management, Firmware, Network Protocols, PCI Express, AI Infrastructure, Graphics Processing Unit (GPU), Computer Network Operations, Application Specific Integrated Circuits, Parallel Computation, Hardware Debugging
- **Published:** September 5, 2026
- **Apply:** https://www.careerbuilder.com/job-details/asic-architect-saratoga-ca--b1c68ffa-cefe-43a1-b2a0-b83c709e1456

## About the Role

* MSEE or equivalent with 10+ years in semiconductors; 5-7 years in ASIC architecture
 * Background in CPUs, GPUs, DPUs, or switches
 * Strong problem-solving and architecture methodology skills
 * Experience with queueing, memory, and scheduling in high-throughput systems
 * Familiar with scalable memory, crossbars, and high-speed datapaths
 * Bonus: knowledge of networking protocols
 * Excellent communication and documentation skills, ASIC (Application Specific Integrated Circuit), Architectural Services, Artificial Intelligence (AI), CPU (Central Processing Unit), Communication Skills, Computer Firmware, Computer Networks, Datapath Design, Debugging Skills, Documentation, GPU (Graphics Processing Unit), High Speed I/O, Memory Hardware, Network Operations Center, Network Protocols, Performance Modeling, Problem Solving Skills, RTL Verification, Silicon Bringup, Startup, Switching Architecture, Systems Scalability

## Description

* Define architectures for high-performance networking ASICs
 * Translate system goals into scalable architecture plans
 * Drive queuing, memory, and scheduling strategies
 * Model and evaluate performance trade-offs
 * Collaborate across RTL, verification, and firmware teams
 * Oversee integration of high-speed I/O and memory interfaces
 * Support post-silicon bring-up and debug, Keywords: ASIC Architect, networking ASIC, switch architecture, system-level architecture, high-throughput systems, queueing, scheduling, memory management, high-speed datapaths, microarchitecture, performance modeling, interface integration, PCIe, SerDes, RTL collaboration, post-silicon validation, MSEE, AI infrastructure, semiconductor design, datapath architecture, parallel processing, hardware startup, AI data center, latency optimization, power efficiency, architectural trade-offs, cross-functional teams, hardware debugging, silicon bring-up, behavioral modeling


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