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# Lead ASIC DFT Staff Engineer

- **Company:** The Aes Group, Inc
- **Location:** Allen, TX, United States (Remote available)
- **Experience:** Expert
- **Salary:** $107,480.0 - $143,307.0
- **Contract:** Permanent contract
- **Skills:** Code Coverage, Software Debugging, Electronic Design Automation, Perl (Programming Language), Joint Test Action (IEEE Standards), Python (Programming Language), Tcl (Programming Language), Scripting, Application Specific Integrated Circuits, Physical Design
- **Published:** September 5, 2026
- **Apply:** https://www.careerjet.com/jobad/us2d9e3b50685dc832815cc599d8569e9d

## About the Role

* 8+ years of hands-on ASIC DFT experience
 * Strong expertise in Scan, ATPG, MBIST/LBIST & DFT debug
 * Experience with Synopsys, Cadence and/or Siemens/Mentor EDA tools
 * Hands-on experience with scan insertion, ATPG, DRC & coverage analysis
 * Experience with MBIST implementation/verification; SMS preferred
 * Strong post-silicon debug and silicon bring-up experience
 * Experience with large, complex ASIC/SoC designs and hierarchical DFT flows
 * Strong understanding of RTL, synthesis, LEC and physical design
 * Scripting experience with Tcl, Perl or Python

## Description

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield., * Lead DFT architecture, implementation, verification & sign-off

 * Drive scan architecture, scan insertion, scan stitching & compression
 * Own ATPG, MBIST/LBIST, DRC, coverage & diagnosis
 * Work with JTAG, Boundary Scan, iJTAG & SSN
 * Develop and validate DFT SDC and timing constraints
 * Lead silicon bring-up, post-silicon debug & root-cause analysis
 * Collaborate with RTL, Verification, Physical Design, STA & Silicon teams
 * Develop DFT automation using Tcl, Perl or Python
 * Mentor DFT engineers and drive best practices


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