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# ELECTRONIC FPGA ENGINEER - HUBER+SUHNER

- **Company:** Huber+suhner
- **Location:** Cambridge, UK
- **Contract:** Permanent contract
- **Skills:** Board Bringup, Adobe InDesign, Configuration Management, Code Coverage, Code Review, Computer Engineering, Software Debugging, Firmware, Field-Programmable Gate Array (FPGA), Hardware Interface Design, Subversion, Systems Integration, Tcl (Programming Language), Universal Asynchronous Receiver/Transmitter, VHSIC Hardware Description Language (VHDL), Vivado, Scripting, State Machines, Software Coding, Software Version Control
- **Published:** September 7, 2026
- **Apply:** https://www.apply4u.co.uk/jobs/electronic-fpga-engineer-hubersuhner/46386273

## About the Role

analysis; achieve timing closure and generate production-ready bitstreams.Contribute to requirements capture, architecture design, module specifications, and DFT/DFM considerations for FPGA-based systems.Maintain configuration management (SVN), branching/release processes, and traceability to requirements.Produce and maintain technical documentation: design descriptions, registers/interfaces, test procedures, and change logs.Participate in design and code reviews, support system integration, and assist production/field teams with issue triage.Support continuous improvement of FPGA design flows, test coverage, and automation (e.g., Tcl/Python scripts).Your profileDegree or equivalent experience in Electronic/Electrical Engineering, Computer Engineering, or related discipline.Strong hands-on experience with VHDL for FPGA design and verification.Proven experience targeting Xilinx Artix-7 families; confident using Vivado (project setup, constraints, synthesis, place & route, timing closure,
bitstream generation).Ability to design deterministic finite state machines (FSMs) for control/driver logic.Experience implementing and validating low-level embedded interfaces: I²C, SPI, UART (desirable), including bus arbitration, timing, and protocol edge cases.Competence in writing self-checking test benches and performing simulation (e.g., using Vivado simulator).Experience testing on hardware: bringing up boards, using logic analysers/oscilloscopes, debugging timing/constraint issues, and validating firmware in-system.Understanding of timing constraints (XDC), clock domain crossing (CDC), metastability, resets, and synchronous design best practices.Familiarity with version control (e.g., SVN). #J-18808-Ljbffr

## Description

At HUBER+SUHNER, we design and create essential components that transport power and data through networks. This is how our employees around the globe contribute to a world where people get and stay connected.Electronic FPGA EngineerCambridge | 100 | UnlimitedYour tasksDesign & implement FPGA logic in VHDL for Xilinx Artix-7 devices using Vivado, adhering to coding standards and design reviews.Develop finite state machines to control and sequence hardware interfaces and protocols reliably.Create low-level driver logic for I²C, SPI (and other simple serial interfaces), including initialisation, transaction handling, and error conditions.Write and maintain test benches (self-checking where practical), conduct functional and timing simulations, and document verification results.Perform hardware bring-up and validation, including lab testing, measurements, and iterative debug; collaborate on board-level constraints and interface timing.Manage constraints (XDC), clocking, resets, and CDC


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