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# CPU RTL Engineer

- **Company:** Qualcomm
- **Location:** Santa Clara, CA, United States
- **Salary:** $155,000.0 - $200,000.0
- **Contract:** Permanent contract
- **Skills:** Boolean Algebra, Software Debugging, Static Timing Analysis, Verilog, Application Specific Integrated Circuits, Physical Design
- **Published:** September 7, 2026
- **Apply:** https://find.jobs/jobs-near-me/apply/ats-redirect/?id=2953162756-2

## About the Role

* Verilog
 * System
 * Verilog
 * CPU microarchitecture
 * Digital logic design
 * ASIC/So
 * C design flow
 * Static timing analysis
 * RTL simulation and debug
 * Low power design techniques
 * Synthesis tools (e.g., Design Compiler)
 * Computer architecture (pipelines, caches, coherency)

## Description

Qualcomm seeks a CPU RTL Engineer to design and verify high performance processor cores for advanced wireless, 5G, AI, and automotive SoCs. In this role, you will develop micro architecture, write synthesizable RTL, and collaborate closely with verification, physical design, and architecture teams to optimize performance, area, and power. You'll analyze timing, run simulations, debug complex logic issues, and contribute to design reviews and methodology improvements. Join an innovative, fast paced, collaborative culture building next generation telecommunications and media platforms used worldwide., * Design and implement CPU micro architecture for wireless and media So

 * Cs
 * Develop high quality, synthesizable RTL for processor cores and subsystems
 * Collaborate with architecture, verification, and physical design teams to meet PPA goals
 * Run simulations and formal checks to validate functionality and performance
 * Debug complex logic, timing, and integration issues across the CPU pipeline
 * Contribute to design reviews, documentation, and coding best practices
 * Support synthesis, timing closure, and signoff activities
 * Optimize designs for power efficiency, area, and scalability across product lines


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