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# Design For Test Engineer III (IC)

- **Company:** einfochips, Inc.
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $95,900.0 - $170,500.0
- **Contract:** Permanent contract
- **Skills:** Bash Shell, Software Debugging, Perl (Programming Language), Make (Software), Joint Test Action (IEEE Standards), Tcl (Programming Language), Scripting
- **Published:** September 7, 2026
- **Apply:** https://find.jobs/jobs-near-me/apply/ats-redirect/?id=2944988536-2

## About the Role

* 5 - 7 Years of experience in DFT
 * Scan-Insertion, ATPG, GLS, Pattern Simulations (with and w/o timing)
 * MBIST Insertion and Verification
 * Experience in IEEE 1149.1 JTAG Insertion and verification
 * Scripting languages like Perl, Shell, TCL
 * Worked on multi-million gate count SoCs in the area of Networking, Consumer, and various IPs like PLL, Serdes
 * Tools: Mentor Tessent
 * B. Tech, M.Tech in Microelectronics/Electronics
 * Excellent communicator
 * Low power DFT

## Description

* DFT implementation for 3nm and 5nm Networking chips, IP DFT work
 * RTL checks for scan-insertion compatibility using Synopsys Spyglass
 * Scan-Insertion using Tessent TestKompress
 * ATPG pattern generation:
 * Compressed and Uncompressed Mode
 * Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax
 * Pattern Simulation:
 * Without timing, With timing for different corners
 * Tools: VCS
 * Mismatch debug using Verdi
 * Scripting with Perl, Shell, TCL:
 * DAeRT - DFT flow enhancement/automation in project
 * Makefile enhancement using extended scripts and targets for flow enhancement
 * MBIST Insertion and Verification:
 * MBIST Insertion and Verification done on block on top
 * Silicon debug and bring-up done for block and top
 * IEEE 1149.1 JTAG Insertion and verification, Work Arrangement Fully On-Site: Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership.


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