> Markdown version of [/jobs/ext/2821506-senior-staff-design-for-test-engineer](https://www.wearedevelopers.com/jobs/ext/2821506-senior-staff-design-for-test-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Senior/Staff Design for Test Engineer - **Company:** OLIX - **Location:** Bristol, UK - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** 3D Printing, Artificial Intelligence, Macintosh Computers, Code Coverage, Software Debugging, Logic Synthesis of Circuits, Firmware, Joint Test Action (IEEE Standards), Python (Programming Language), Open Source Technology, Rapid Prototyping Process, SystemVerilog, Tcl (Programming Language), Test Execution Engine, Strategies of Testing, Verilog, VHSIC Hardware Description Language (VHDL), Application Specific Integrated Circuits, Hardware Acceleration - **Published:** September 10, 2026 - **Apply:** https://www.collegerecruiter.com/job/2840598809-seniorstaff-design-for-test-engineer ## About the Role * 7+ years of hands-on DFT architecture, implementation, and verification for high-performance ASICs or SoCs, including ownership of at least one product with comprehensive DFT coverage. * Proven success implementing and verifying advanced DFT features (e.g., Scan/ATPG, Boundary Scan, Memory BIST/Repair) on multi-hundred-MHz to multi-GHz clock domains. * Expertise with industry-standard EDA flows: Scan insertion, ATPG, pattern simulation (gate-level), fault modeling, and diagnosis tools. * Demonstrated proficiency with DFT flows: compression techniques, EDT, JTAG/IEEE 1149.1/1687, and managing large pattern sets. * Proficiency using Python/Tcl scripting for DFT flow automation, pattern generation/management, and silicon debug/bring-up. * Solid grounding in semiconductor device physics, fault models (stuck-at, transition, bridging), and yield enhancement strategies. * Excellent communication and cross-functional collaboration abilities; thrives in a fast-moving, ambiguous environment., * Tape-out experience at 22 nm or below. * Knowledge of high-speed SerDes or HBM/DDR DFT challenges. * Familiarity with AI/ML workloads or systolic arrays and their implications for DFT. * Contributions to open-source DFT tools or verification frameworks. ## Description We are seeking highly skilled and motivated Senior/Staff DFT (Design For Test) Engineers with a strong focus on high-performance digital design to take end-to-end ownership of robust, testable silicon-from early test strategy definition to verified DFT implementation, pattern generation, and silicon bring-up. You will join a multidisciplinary group creating next-generation accelerators where digital, optical and mixed-signal domains intersect. The ideal candidate will have extensive experience in the DFT of large-scale, high-volume ASICs, and a passion for developing reliable, high-coverage test architectures that drive breakthrough AI hardware., * Architect, own, and implement the comprehensive Design-for-Test (DFT) strategy for complex high-throughput digital pipelines in advanced CMOS nodes, ensuring high test coverage and efficient test execution. * Lead the integration and verification of all DFT features, including Scan, JTAG, Boundary Scan, and Memory BIST, ensuring adherence to industrial standards and sign-off criteria. * Partner with the test engineering team to develop, validate, and optimize ATE-compatible test patterns (stuck-at, transition, bridging, etc.) to achieve aggressive fault coverage and maximise manufacturing yield. * Drive RTL development (SystemVerilog / Verilog / VHDL) with a focus on DFT architecture, including synthesis constraints for test structures, and collaborate on formal and constrained-random verification of DFT logic. * Analyse and minimise the DFT impact on power, performance, and area (PPA), implementing innovative techniques for efficient test access and execution. * Collaborate with mixed-signal and software teams to define and optimise DFT interfaces, test modes, and firmware abstractions for test control and diagnosis. * Mentor junior engineers, lead DFT design reviews, and champion best-practice methodologies for testability and debug across the ASIC development lifecycle., * Elite Hardware: M4 Macs come as standard, with M4 Pro upgrades for our engineering team. We will provide whatever you need to do your best work. * Optimal Environment: High-spec noise-cancelling headphones and a fully ergonomic workstation designed for deep focus. * Rapid Prototyping: Access to our high-performance 3D printing lab for work, experimentation, and personal creative projects. ## Related Videos - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Playing Pong on a shoulder press machine](https://www.wearedevelopers.com/videos/100140-playing-pong-on-a-shoulder-press-machine) - [How I built my own intelligent Robot Arm from Scratch](https://www.wearedevelopers.com/videos/100097-how-i-built-my-own-intelligent-robot-arm-from-scratch) - [Building your way to a serverless powered IOT Buzzwire game](https://www.wearedevelopers.com/videos/590-building-your-way-to-a-serverless-powered-iot-buzzwire-game) - [Agent Smith Gets Hardware: Autonomous IoT Hacking From Debug Port to Cloud API](https://www.wearedevelopers.com/videos/100258-agent-smith-gets-hardware-autonomous-iot-hacking-from-debug-port-to-cloud-api) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) ## Related Articles - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [The 8 Best Code Testing Tools](https://www.wearedevelopers.com/magazine/402-the-8-best-code-testing-tools) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers) - [Should senior developers refuse interview coding challenges?](https://www.wearedevelopers.com/magazine/29-should-senior-developers-refuse-interview-coding-challenges) - [Why developer experience matters](https://www.wearedevelopers.com/magazine/514-why-developer-experience-matters) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers)