> Markdown version of [/jobs/ext/2822289-principal-power-delivery-engineer-ai-system](https://www.wearedevelopers.com/jobs/ext/2822289-principal-power-delivery-engineer-ai-system). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Principal Power Delivery Engineer - AI System - **Company:** Hyve Solutions - **Location:** Portland, OR, United States - **Experience:** Expert - **Salary:** $214,000.0 - $290,000.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, Firmware, Software Reliability Testing - **Published:** September 10, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=f63824dd2f52b2d7 ## About the Role * Education: Bachelor's or Master's in Electrical Engineering or a related field. * Experience: 10+ years of power delivery / VRM design experience for servers, GPU platforms, or high-power electronics, with proven delivery of high-current designs into production. * Technical expertise: Deep knowledge of DC/DC conversion, multiphase VR design, 48V/54V architectures, PDN design and analysis, magnetics, and power component selection; experience with power simulation and bench characterization (electronic loads, oscilloscopes, thermal tools). * Systems knowledge: Understanding of power sequencing, telemetry, protection, and the interaction of power delivery with thermal, SI, and firmware/BMC domains. * Communication: Able to lead trade-off discussions and clearly present power architecture decisions to technical leaders and customers. ## Description * Power architecture. Define end-to-end power delivery architecture for AI/GPU platforms, including 48V/54V direct conversion, intermediate bus, VRM/PMIC topologies, and point-of-load regulation for high-current rails. * VR and PDN design. Design and specify multiphase voltage regulators, select power stages, controllers, inductors, and capacitors, and drive PDN design in partnership with SI/PI and layout teams to meet impedance, transient, and IR-drop targets. * Efficiency and telemetry. Optimize conversion efficiency, thermal footprint, and power density; define power sequencing, telemetry, and protection strategies in coordination with firmware/BMC teams. * Validation and bring-up. Lead power bring-up and validation across EVT/DVT/PVT, including load-line, transient, efficiency, and reliability testing; correlate bench results and drive corrective actions. * Cross-functional leadership. Guide board designers, thermal, mechanical, and firmware teams on power-related trade-offs, set design methodology, and mentor engineers on power delivery best practices.