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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # CPU Subsystems RTL Design Engineer, AI Hardware - **Company:** Tesla Motors - **Location:** Palo Alto, CA, United States - **Experience:** Expert - **Salary:** $188,000.0 - $312,000.0 - **Contract:** Permanent contract - **Skills:** Artificial Intelligence, ARM Architecture, Computer Engineering, Computer Telephony Integration, Software Debugging, Multiplexing, Microprocessors, Fault Tolerance, Firmware, Subsystems, SystemVerilog, Systems Integration, Verilog, Network Switches, Application Specific Integrated Circuits, Hardware Acceleration, Physical Design - **Published:** September 10, 2026 - **Apply:** https://diversityjobs.com/main/sendform/8/8/28176/1/18239308?backUrl=%2Fcareer%2F18239308%2FCpu-Subsystems-Rtl-Design-Engineer-Ai-Hardware-California-Palo-Alto ## About the Role * Degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent experience * 7+ years of experience in ASIC RTL design using Verilog or SystemVerilog * Strong hands-on experience integrating ARM Cortex-A series CPUs (Armv8-A and/or Armv9-A) and ARM interrupt controllers (GIC-400, GIC-600, GIC-700 or equivalent), including distributor/redistributor configuration and ITS into production SoCs. * Expertise in cache coherency protocols, specifically AMBA CHI and/or ACE/ACE-Lite, including snoop transactions, coherency states, and ordering/barrier semantics * Working knowledge of CoreSight debug architecture, including CTI/CTM cross-triggering, trace funnels and sinks, and debug authentication * Hands-on experience with PLLs, clock dividers, glitch-free clock muxing, and clock gating to generate and manage the multiple clocks required by a CPU subsystem, including support for DVFS schemes * Familiarity with UPF-based low-power design flows, including power domain partitioning for CPU clusters, isolation and level-shifter strategy, retention, and power state tables * In-depth knowledge of multi-clock domain handling and clock domain crossing * Experience with SoC reset and power-domain architectures, reset sequencing, and safe reset propagation across domains ## Description In this role, you will own CPU subsystem integration, cache-coherent interconnect architecture, and SoC-level debug and trace infrastructure within our custom ASICs. You will work closely with cross-functional teams to deliver innovative hardware solutions that push the boundaries of performance, efficiency, and reliability in AI applications. You are expected to define and document microarchitecture specifications for CPU and interconnect integration, set system-level functional requirements for coherent memory traffic, and deliver high-quality RTL designs optimized for AI workloads. What You'll Do * Own end-to-end integration of ARM Cortex-A class CPU clusters (Armv8-A / Armv9-A) into custom AI SoCs, including cluster configuration, memory map definition, and boot architecture * Architect and integrate the interrupt subsystem, including GIC (GICv3/GICv4) configuration, LPI/ITS support, message-signaled interrupts, and interrupt routing and affinity across cores * Define and implement CPU cluster harvesting for yield recovery, including fuse-based core/cluster disable, boot-time configuration of active core sets, and correct enumeration of harvested topologies to interconnect, GIC, and debug infrastructure * Design and implement RTL for coherent interconnect integration, ensuring correct and high-performance CHI or ACE/ACE-Lite connectivity between CPU clusters, accelerators, and memory subsystems * Implement and validate CoreSight debug and trace infrastructure, including CTI/CTM cross-triggering, ETM/ETB/TMC trace paths, timestamping, and APB debug access * Optimize CPU-to-memory and CPU-to-accelerator data paths for latency, bandwidth, and coherency overhead, including snoop filter sizing, cache maintenance flows, and DMA interaction * Develop and optimize SoC clocking architectures for CPU subsystems, including multi-domain clock distribution, DVFS support, synchronization, and power-efficient clock gating * Architect and implement reset and power-domain sequencing for CPU clusters, including core power-down/warm reset flows, reset domain crossing, and fault-tolerant recovery * Partner with architecture, firmware, and verification teams to define and refine CPU subsystem microarchitecture, and represent the CPU subsystem in SoC-level architecture decisions * Drive timing and power closure for the CPU complex in partnership with the physical design team, including RTL restructuring, pipeline adjustments, and hierarchy/floorplan feedback ## Related Videos - [Unleashing the Full Potential of the Arm Architecture – Write Once, Deploy Anywhere](https://www.wearedevelopers.com/videos/940-unleashing-the-full-potential-of-the-arm-architecture-write-once-deploy-anywhere) - [Playing Pong on a shoulder press machine](https://www.wearedevelopers.com/videos/100140-playing-pong-on-a-shoulder-press-machine) - [10M Data Records Lost, Underwater Computing, and Psychedelic Fish - Matthias Geniar](https://www.wearedevelopers.com/videos/1908-10m-data-records-lost-underwater-computing-and-psychedelic-fish-matthias-geniar) - [Building a hypercar from scratch](https://www.wearedevelopers.com/videos/607-building-a-hypercar-from-scratch) - [Agent Smith Gets Hardware: Autonomous IoT Hacking From Debug Port to Cloud API](https://www.wearedevelopers.com/videos/100258-agent-smith-gets-hardware-autonomous-iot-hacking-from-debug-port-to-cloud-api) - [Develop on Windows, Deploy on Red Hat Enterprise Linux](https://www.wearedevelopers.com/videos/1600-develop-on-windows-deploy-on-red-hat-enterprise-linux) ## Related Articles - [How software is steering vehicle technology](https://www.wearedevelopers.com/magazine/515-how-software-is-steering-vehicle-technology) - [AI Eats the Verifiable First](https://www.wearedevelopers.com/magazine/765-ai-eats-the-verifiable-first) - [Dev Digest 120 - Apple and peers](https://www.wearedevelopers.com/magazine/455-dev-digest-120-apple-and-peers) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [How to Become an AI Engineer](https://www.wearedevelopers.com/magazine/331-how-to-become-an-ai-engineer) - [Dev Digest 132 - Binging WADFlix?](https://www.wearedevelopers.com/magazine/473-dev-digest-132-binging-wadflix)