> Markdown version of [/jobs/ext/2834853-fpga-programmer](https://www.wearedevelopers.com/jobs/ext/2834853-fpga-programmer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # FPGA Programmer - **Company:** Rajant Corporation - **Location:** Malvern, PA, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** C (Programming Language), Adobe InDesign, ARM Architecture, Bash Shell, Bluetooth, Boolean Algebra, C++ (Programming Language), Software Documentation, Computer Programming, Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Ethernet, Field-Programmable Gate Array (FPGA), Hardware Description Language, IPv4, IPv6, Python (Programming Language), Mesh Networking, Static Timing Analysis, System on a Chip, SystemVerilog, Systems Integration, Tcl (Programming Language), Verilog, Vivado, Scripting, Software Verification, Fpga Hardware, ModelSim, Information Technology - **Published:** September 10, 2026 - **Apply:** https://www.indeed.com/viewjob?jk=7193b21c6c1ead27 ## About the Role * Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Systems, or related technical field. * Approximately 5+ years of professional FPGA or digital logic design experience. * Verilog/System design experience with 1G/2.5G/5G/10G Multirate PHY and MAC IP * Experience with L2/L3/L4 Ethernet protocols * Strong Verilog RTL coding and verification skills; experience with SystemVerilog and FPGA test bench development. * Hands-on experience with Xilinx/AMD Vivado, Intel/Altera Quartus, or similar FPGA development tools. * Strong knowledge of synthesis, Static Timing Analysis (STA), HDL simulation, timing constraints, and timing debug. * Understanding of System-on-Chip (SoC) architectures, embedded processors, and multi-clock-domain design. * Experience with hardware/software integration, FPGA debugging, and independent problem solving. * Ability to work effectively within a small, multidisciplinary engineering team., * Experience developing FPGA solutions for embedded networking, wireless communications, or security-related products. * Familiarity with wireless waveforms such as 802.11, Bluetooth, LoRA, Wi-SUN * Familiarity with ARM processor architectures and embedded SoC platforms. * Familiarity with Ethernet, IPv4/IPv6, and embedded interfaces such as QSPI, MMC, I2C, or DDR. * Experience with Mentor ModelSim or similar HDL simulation and verification tools. * Programming or scripting experience with C, C++, Python, Tcl, Bash, or similar languages. * Experience with FPGA/SoC product bring-up and products for defense, industrial, or other mission-critical applications. * Current or previous U.S. Government security clearance is a plus. ## Description Rajant is seeking an experienced FPGA Programmer to develop and support FPGA-based solutions for our industry-leading wireless mesh networking products. This hands-on role focuses on FPGA logic design, implementation, verification, debugging, and integration within embedded and System-on-Chip (SoC) platforms. You'll work closely with FPGA, software, systems, and hardware engineers to develop reliable, high-performance programmable logic for Rajant's embedded networking products., * Design, develop, implement, and maintain FPGA logic using Verilog and SystemVerilog. * Implement designs using industry-standard FPGA development tools and vendor tool flows. * Develop RTL logic for embedded and System-on-Chip (SoC) architectures. * Create and maintain Verilog/SystemVerilog test benches and verification test suites. * Define and implement timing constraints; perform synthesis, simulation, implementation, verification, and Static Timing Analysis (STA). * Develop and debug FPGA designs involving multiple clock domains and embedded interfaces. * Support FPGA and product bring-up, testing, debugging, and troubleshooting. * Participate in design reviews and contribute to technical and system documentation.