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# Design Engineer I

- **Company:** Cadence Design Systems, Inc.
- **Location:** San Jose, CA, United States
- **Experience:** Starter
- **Salary:** $88,900.0 - $165,100.0
- **Contract:** Permanent contract
- **Skills:** Analog Electronics, Automation of Tests, Software Debugging, Digital Electronics, Logic Synthesis of Circuits, Perl (Programming Language), Python (Programming Language), Scripting
- **Published:** May 14, 2026
- **Apply:** https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Design-Engineer-I_R54745-2

## About the Role

* The candidate is expected to be strongly motivated by the prospect of driving electrical testing efforts for identifying silicon issues and being involved in debug efforts for the same.
 * Very good fundamentals in analog electronics, digital electronics, negative feedback theory, stability and control systems theory
 * Strong analytical and problem-solving skills
 * The role is open for candidates with Bachelor's or Master's degree in Electrical Engineering with 0-2 years of relevant work experience
 * Excellent written and verbal communication skills
 * Ability to work collaboratively in a team environment
 * Prior experience in the hardware semiconductor or electronics industry is a plus
 * Experience with script-based test automation in Perl, Python, or other scripting tools is a plus

## Description

This is a full-time, on-site role for a Post Silicon Electrical Validation Engineer (grade T1) based in San Jose, CA, in the Cadence IP group. The engineer will be responsible for validating the electrical performance of our internal silicon test chips, debugging silicon issues by collaborating with the analog and digital design teams and releasing high quality characterization reports. The role involves collaborating with cross-functional teams to ensure the reliability and functionality of the product.


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