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# Digital Verification Engineer

- **Company:** ETHAN ALEXANDER GROUP INC.
- **Location:** Campbell, CA, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Software Debugging, Oracle Virtual Machine, SystemVerilog, Verilog, VHSIC Hardware Description Language (VHDL)
- **Published:** September 11, 2026
- **Apply:** https://www.thejobnetwork.com/job/00c6d7e2-60e0-4cb4-a14c-89f8f489c8da/digital-verification-engineer-

## About the Role

* Proficiency in verification test planning, test bench architecture, assertions, problem solving and debugging
 * Constrained random verification experience with System Verilog using OVM or UVM
 * Set up coverage driven verification (code/functional/assertion coverage)
 * Strong knowledge of Verilog or VHDL
 * BS or MS (preferred) degree in EE or equivalent, with 5+ years of experience

Nice to Have:

 * Experience in testbenches (block, system) and setting up verification flow from ground-up
 * Understands secure/non-secure, interrupts, memory, and clock frequency switching
 * Familiar with low-power designs, understands power saving techniques and verifications
 * Wireless communications, knowledge of BLE at the protocol level

## Description

* Develop test plans and verification infrastructure for low-power ASIC designs
 * Build verification environments using SV/UVM methodology
 * Build reusable bus functional models, drivers, monitors, checkers and scoreboards
 * Debug/triage automated regressions, run gate level simulations, and perform coverage analysis


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