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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Principal Engineer, Hardware Application Engineering - **Company:** CUSTOMER SOLUTIONS GROUP - **Location:** Santa Clara, CA, United States - **Experience:** Expert - **Salary:** $200,000.0 - $266,400.0 - **Contract:** Permanent contract - **Skills:** Board Bringup, Artificial Intelligence, Computer Engineering, Data Centers, Software Debugging, Electronic Design Automation, Ethernet, Hardware Design, PCI Express, Software Reliability Testing, Network Switches, Computer Networking Systems - **Published:** September 11, 2026 - **Apply:** https://www.thejobnetwork.com/job/9df4a61d-600d-4d5f-903b-795d2944b313/sr-principal-engineer-application-engineering-system-design ## About the Role * Education: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a related field. * Overall Experience: 15+ years in hardware design, development, and validation of high-speed networking or compute systems. * SerDes Expertise: 7+ years of dedicated experience in board and system design for high-speed platforms involving modern SerDes (25G NRZ through 112G/224G PAM4). * Board Lifecycle: Proven full-lifecycle ownership of complex high-speed boards (architecture, schematic, layout guidance, bring-up). * Reference Designs: Demonstrated experience defining and delivering reference designs that enabled customer or internal platform adoption. * Technical Depth: + Strong expertise in high-layer-count PCB stack-up design and material selection. + Deep experience with power architecture for high-current ASICs (PDN design, sequencing, decoupling, tolerance analysis). + Solid background in thermal design and mechanical integration for high-power network/AI systems. + Working knowledge of SI/PI principles (ability to review and run targeted simulations). + Hands-on lab experience with hardware bring-up, debugging, and root-cause analysis using industry-standard equipment. + Deep understanding of high-speed interfaces: Ethernet, PCIe, DDR, advanced SerDes, and modern power delivery. * * Soft Skills & Leadership: + Proven customer-facing experience supporting complex technical engagements. + Ability to develop and deliver technical training to engineering audiences. + Exceptional communication skills with a track record of influencing senior customer engineering teams across geographies., * Direct experience with Ethernet switch platforms (any tier) and/or emerging open AI fabric standards. * Experience designing or reviewing hardware platforms targeting megascale data center deployments. * Background in reference platform design and customer enablement for silicon-based solutions. * Familiarity with ODM/CM manufacturing flows, including DFM/DFT, qualification, and reliability testing. * Experience with advanced cooling approaches (liquid, immersion) for high-power AI/networking platforms. * Fluency with EDA tools in either Cadence (Allegro/Sigrity) or Mentor/Siemens (Xpedition/HyperLynx) ecosystems (tool-agnostic experts are welcome). * Track record of influencing silicon and platform roadmaps based on field insights. Leadership, Impact & Work Environment * Leadership & Mentorship: Set the technical bar for board and system design quality across the most strategic customer engagements; mentor engineers and raise collective team expertise. * Travel: Project-driven travel to customer sites, ODMs, and labs as needed (not continuous). ## Description As Senior Principal Engineer for Board & System Hardware Design, you will serve as the senior technical authority guiding customer hardware design-in on proprietary Ethernet Switch and UALink platforms. You will act as the crucial technical bridge between internal silicon teams, hardware engineering, and field operations. This is a deep individual contributor role with a strong system-design and productization focus. Your primary mission is to ensure that customers' next-generation switches, AI fabric platforms, and networking systems are designed right the first time-performant, manufacturable, reliable, and ready for high-volume production. Key ResponsibilitiesTechnical Leadership & Customer EnablementSystem Architecture & Hardware Design Guidance * Drive PCB stack-up strategy and material selection (low-loss laminates, copper roughness, glass weave, via construction) to meet high-speed performance and cost targets. * Guide customers on power delivery architecture, including PDN design, multi-rail sequencing, decoupling strategy, and tolerance analysis for high-current ASICs. * Advise on thermal design, mechanical integration, and cooling strategies (air, liquid, immersion) to meet performance and reliability targets in real deployments. * Provide guidance on signal and power integrity (SI/PI), reviewing customer simulations and contributing simulations directly when required. * Drive Design for Reliability, Manufacturability, and Testability (DFx)-ensuring smooth transitions to production at ODM/CM partners. Next-Gen Tech & Cross-Functional Influence * Provide technical leadership on 112G and 224G PAM4 SerDes designs today, and help shape the hardware approach for next-generation 448G systems and open AI fabric standards. * Lead hardware bring-up support, root-cause debug, and issue resolution during customer lab phases and early production. * Act as a vital field-feedback channel to internal silicon and hardware teams-influencing silicon I/O, package, power, and reference design choices based on real-world customer deployment learnings., * Serve as the primary senior technical advisor to customer hardware teams designing platforms around company Ethernet switches and UALink silicon from early architecture through production ramp. * Lead design-in reviews of customer schematics, PCB stack-ups, and overall system architectures, identifying risks early and guiding customers to best-in-class implementations. * Define, develop, and support reference designs for new silicon-partnering with silicon, packaging, and internal hardware engineering teams from early product definition through customer release. * Own architecture, schematic, layout guidance, and bring-up of company reference and evaluation platforms, applying full lifecycle hands-on expertise. * Develop and deliver high-impact technical training to customers and internal teams covering proprietary silicon, reference designs, high-speed design best practices, and productization methodologies. ## Related Videos - [The Gashlycrumb Tinies of AI Networking You Must Know (or Languish!)](https://www.wearedevelopers.com/videos/2067-the-gashlycrumb-tinies-of-ai-networking-you-must-know-or-languish) - [The Sustainability Race: AI's Promises, Pitfalls and Potential](https://www.wearedevelopers.com/videos/100155-the-sustainability-race-ai-s-promises-pitfalls-and-potential) - [Breaking the Hardware Mindset: Overcoming Barriers to System-Level Innovation](https://www.wearedevelopers.com/videos/1635-breaking-the-hardware-mindset-overcoming-barriers-to-system-level-innovation) - [Building a hypercar from scratch](https://www.wearedevelopers.com/videos/607-building-a-hypercar-from-scratch) - [Building the Nervous System of AI - Michael Kagan (NVIDIA)](https://www.wearedevelopers.com/videos/2133-building-the-nervous-system-of-ai-michael-kagan-nvidia) - [Docker network without Docker](https://www.wearedevelopers.com/videos/1418-docker-network-without-docker) ## Related Articles - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [What Makes WeAreDevelopers World Congress Different From Every Other Tech Event?](https://www.wearedevelopers.com/magazine/701-what-makes-wearedevelopers-world-congress-different-from-every-other-tech-event) - [Top Characteristics of a Software Engineer](https://www.wearedevelopers.com/magazine/166-top-characteristics-of-a-software-engineer) - [Highest Paying Tech Companies for Developers](https://www.wearedevelopers.com/magazine/220-highest-paying-tech-companies-for-developers) - [How Engineering Hubs Build Visibility at Developer Conferences like WeAreDevelopers World Congress](https://www.wearedevelopers.com/magazine/720-how-engineering-hubs-build-visibility-at-developer-conferences-like-wearedevelopers-world-congress) - [What is Software Engineering?](https://www.wearedevelopers.com/magazine/289-what-is-software-engineering)