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# Senior CPU Architecture and Performance Architect

- **Company:** Google LLC
- **Location:** Portland, OR, United States
- **Experience:** Expert
- **Salary:** $192,000.0 - $278,000.0
- **Contract:** Permanent contract
- **Skills:** Software Bug Management, Computer Engineering, Microarchitecture, Software Debugging, Linux, Reduced Instruction Set Computing, Information Technology, Instruction Set Architecture, Physical Design
- **Published:** September 11, 2026
- **Apply:** https://dejobs.org/x/x/2279E35DFA6741029B6CB76696893E10/job/

## About the Role

Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain., * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.

 * 10 years of experience in microprocessor architecture, microarchitecture, performance and design.
 * Experience with CPU architecture with CPU blocks, along with performance modeling, analysis, correlation, and workload characterization.
 * Experience with processor instruction set architecture (e.g., ARM, RISC-V, x86) and system software components, such as Linux, drivers, and runtime., * Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
 * Experience in performance modeling, debugging, and demonstrating the benefits of new ideas.
 * Knowledge of processor instruction set architecture (e.g., ARM, RISC-V, x86).
 * Ability to generate innovative microarchitectural ideas to improve performance in actual silicon.
 * Strong critical thinking, communication, and advocacy skills.

## Description

* Deliver solutions to complex problems that may be ambiguous and/or lacking clear precedent. These problems include CPU performance, microarchitecture design, tool infrastructure, methodology, and so on.
 * Plan, drive, and evaluate ARM's architecture features from both architecture and performance angles.
 * Define and write CPU subsystem architecture specifications.
 * Lead the collaboration with RTL, design verification, and physical design teams to develop a high performance and efficient CPU implementation.
 * Drive performance correlation between the performance model and RTL implementation and perform pre-silicon and post-silicon performance bug triage.


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