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# Sr. System Performance Architect- OS Modelling and Simulation

- **Company:** Huawei
- **Location:** Cambridge, UK
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Collaborative Software, Microarchitecture, Performance Tuning, Software Architecture, Quick EMUlator (QEMU), Information Technology, Modeling and Simulation, Hardware Acceleration
- **Published:** September 14, 2026
- **Apply:** https://www.diversifying.io/jobs/593902183-sr-system-performance-architect-os-modelling-and-simulation-at-huawei

## About the Role

* Master's degree or higher in IC, Microelectronics, Computer Science, Communication, or related fields. Relevant experience with practical project work in chip performance modeling, simulation, and collaborative software-hardware optimization.

 * Proficiency in system performance modeling and simulation tools (e.g., gem5, QEMU), with the ability to develop and maintain gem5 simulators.

 * Deep understanding of the chip design process, with the capability to analyze and optimize chip performance.

 * Expertise in software and hardware co-design methodologies to optimize system-level performance.

 * Strong knowledge of benchmark construction and microarchitecture design, with the ability to guide CPU microarchitecture optimization.

## Description

You will spearhead advanced system performance modelling and simulation, seamlessly integrating software and hardware to boost efficiency and maintain a competitive edge. By identifying execution hotspots, evaluating performance metrics, driving software-hardware co-optimization, and utilizing tools like gem5, you will lead the way in innovating CPU microarchitecture design, enhancing product performance, and advancing energy efficiency. This role is pivotal in crafting systems that deliver exceptional user experiences and set benchmarks for sustainable excellence.

Main Responsibilities:

 * Perform system performance modeling and simulation, ensuring the collaborative optimization of software and hardware.

 * Identify program execution hotspots and microarchitecture bottlenecks through top-down analysis of computing load requirements and bottlenecks in key service scenarios, guiding software architecture optimization and hardware acceleration implementation.

 * Develop performance models for the software load and hardware/chip architecture of terminal systems, creating evaluation models for user experience performance indicators based on software load and hardware specifications, and supporting chip and product planning performance evaluations.

 * Lead the development and maintenance of the gem5 emulator to evaluate and optimize system performance in detail.

 * Build benchmarks tailored to terminal software characteristics and guide CPU microarchitecture design, vertically optimizing soft and hard cores to enhance product performance and energy efficiency competitiveness.


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