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# ASIC Design for Test Consulting Engineer

- **Company:** Kforce Inc.
- **Location:** Carlsbad, CA, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Computer Engineering, Software Debugging, Electronic Design Automation, Hardware Design, Joint Test Action (IEEE Standards), Cloud Services, Systems Integration, Application Specific Integrated Circuits, Physical Design
- **Published:** September 15, 2026
- **Apply:** https://www.dice.com/job-detail/124a920e-e358-4929-9967-da14f0d6c642

## About the Role

* Bachelor's or a Master's degree in Electrical or Computer Engineering required, with at least 8-10 years of experience
 * Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and integrating 3rd party IP's and high-speed digital/analog macros
 * Experience with ATPG and EDA tools like Tessent tool sets, Xcelium, Genus, TempPrimetime
 * At least one project with hands-on post-silicon debug of DFT patterns - scan, mbist, boundary scan and release to production
 * The ability to craft solutions and debug with minimal mentorship

Nice to Have:

 * Excellent communication and presentation skills
 * Strong attention to detail and system level understanding of networking and photonic solutions
 * Strong ability to establish/refine, train teams on DFT methodologies - from design phase to high volume production
 * Ability to quickly learn new concepts and adapt to evolving technologies

## Description

Kforce is immediately seeking an experienced ASIC Design for Test Consulting Engineer to remotely support our enterprise networking and cloud solutions customer based in Carlsbad, CA., * Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debug

 * Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL
 * Along with the DFT team, you will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies


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