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# RTL Design Engineer

- **Company:** Tetriq Solutions
- **Location:** Saratoga, CA, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Microarchitecture, Ethernet, Firmware, Network Troubleshooting, Network Protocols, Performance Tuning, SystemVerilog, Verilog, Application Specific Integrated Circuits, Software Troubleshooting
- **Published:** September 15, 2026
- **Apply:** https://www.dice.com/job-detail/81a48d51-6751-473e-b492-a990c51784f2

## About the Role

* knowledge of SystemVerilog and Verilog is mandatory.
 * Good understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments.
 * Experience in designing and optimizing scheduling and QoS mechanisms.
 * Experience with Ethernet and IP protocols.
 * Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging networking issues.

## Description

* Packet buffering, queuing, and scheduling: Work on micro architecture and design implementation of high-speed networking ASIC's, focusing on latency optimization and quality of service (QoS) support. Experience with on-chip memory subsystem and scheduling / arbitration design.
 * Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks. Work with verification team to conduct thorough testing and validation to ensure functionality and reliability.
 * Performance Optimization: Analyze and optimize pipelining architectures to improve performance metrics.
 * Protocol Support: Provide support for various networking protocols such as Ethernet and IP protocols, and high speed interconnects such as UCIe.
 * Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing, working closely with cross-functional teams, including system architects, hardware engineers, and firmware developers.