> Markdown version of [/jobs/ext/2923959-principal-rtl-design-engineer-io-memory-systems](https://www.wearedevelopers.com/jobs/ext/2923959-principal-rtl-design-engineer-io-memory-systems). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Principal RTL Design Engineer, IO & Memory Systems - **Company:** Greenhouse Software, Inc. - **Location:** San Jose, CA, United States - **Experience:** Expert - **Salary:** $180,000.0 - $255,000.0 - **Contract:** Permanent contract - **Skills:** Code Review, Network Congestion, Microarchitecture, Logic Synthesis of Circuits, Ethernet, Machine Learning, PCI Express, Subsystems, SystemVerilog, Application Specific Integrated Circuits, Information Technology, Front End Software Development, Physical Design, Code Restructuring - **Published:** September 15, 2026 - **Apply:** https://boards.greenhouse.io/embed/job_app?for=sambanovasystems&token=6173852004 ## About the Role * MS in Electrical Engineering, Computer Science, or a related field * 7+ years of experience in ASIC design * Experience in logic design, microarchitecture, specification, SystemVerilog RTL design, and functional verification * Experience with power, performance, or area optimization * Experience with two or more on-chip or chip-to-chip protocols and interfaces such as AXI, APB, PCIe, Ethernet, or UCIe * Experience with memory subsystems such as HBM and CXL * Ability to evaluate and select vendor IP, and to read and distill complex IP and protocol specifications into actionable design requirements * Clear and effective communicator with a proactive, collaborative approach to problem-solving, * Experience taking one or more ASIC products from concept to silicon * Familiarity with emerging scale-up protocols (ESUN, SUE, UAL) and scale-out protocols such as Ultra Ethernet * Experience designing on-chip interconnect and traffic-management logic, including NoC fabrics, switches, arbiters, and quality-of-service or congestion control mechanisms * Knowledge of machine learning and hardware accelerator architectures ## Description SambaNova is seeking a Principal Engineer to own the design, integration, and implementation of high-speed IO and memory subsystems within the DataScale® platform. This role is central to delivering reliable, high-performance AI systems at scale. You will drive these subsystems across the full product lifecycle, from architecture exploration and microarchitecture definition through RTL and integration of internal and third-party IP (PCIe, Ethernet , CXL, HBM, die-to-die). This is a hands-on role for an engineer with deep protocol and RTL expertise, who can operate in ambiguity and execute with high ownership., * Engage in architecture exploration with system and chip architects to define IO and memory subsystem direction * Drive feasibility studies and design trade-off analysis to meet PPA constraints * Own microarchitecture definition and specification for IO and memory subsystems * Deliver synthesizable, high-quality SystemVerilog RTL for assigned blocks against functionality, performance, and power targets * Run the front-end design flow end to end, covering lint, CDC/RDC, synthesis, timing constraint development, and design-for-test readiness * Partner with STA and physical design teams on timing closure, floorplanning, congestion analysis, and optimization at advanced process nodes * Work closely with verification and emulation teams to ensure design validation coverage and quality * Collaborate with software and firmware teams to ensure optimal end-to-end solutions * Drive cross-functional triage of complex functional and performance issues to root cause and closure * Apply engineering best practices including code review, testing, and refactoring * Improve design and integration methodology, reuse, and flow scalability ## Related Videos - [The Gashlycrumb Tinies of AI Networking You Must Know (or Languish!)](https://www.wearedevelopers.com/videos/2067-the-gashlycrumb-tinies-of-ai-networking-you-must-know-or-languish) - [Are Code Reviews Worth It? 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