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# Digital Design Verification Engineer

- **Company:** Broadcom
- **Location:** San Jose, CA, United States
- **Experience:** Expert
- **Salary:** $101,000.0 - $162,000.0
- **Contract:** Permanent contract
- **Skills:** Software Debugging, Logic Synthesis of Circuits, Physical Design
- **Published:** September 15, 2026
- **Apply:** https://broadcom.wd1.myworkdayjobs.com/External_Career/job/USA-CA-San-Jose-Innovation-Drive/Digital-Design-Verification-Engineer_R027103

## About the Role

The ideal candidate has a proven track record of working on setting up testbenches for Design Verification using UVM on large designs., * BSEE required, MSEE/PHD preferred

 * 5+ years of industry experience with a focus on SoC integration, UVM test bench setup and design debug.

## Description

* Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off
 * Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule
 * High proficiency in UVM


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