> Markdown version of [/jobs/ext/2932413-asic-dft-engineer](https://www.wearedevelopers.com/jobs/ext/2932413-asic-dft-engineer). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # ASIC DFT Engineer - **Company:** Broadcom - **Location:** Fort Collins, CO, United States - **Experience:** Expert - **Salary:** $109,700.0 - $175,500.0 - **Contract:** Permanent contract - **Skills:** Data Analysis, Software Debugging, Ethernet, PCI Express, Broadcom, Statistical Process Control (SPC), Verilog, Application Specific Integrated Circuits, Yield Optimization, Physical Design - **Published:** September 16, 2026 - **Apply:** https://broadcom.wd1.myworkdayjobs.com/External_Career/job/USA-Colorado-Fort-Collins-4380-Ziegler-Road/ASIC-DFT-Engineer_R025568 ## About the Role The candidate would be required to work on various phases of SoC DFT related activities for APD's designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers., * Bachelors and 8+ years of related experience; or Masters degree and 6+ years of related experience * Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others) * Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.) * Logic BIST design and debug experience * Well-versed in ATPG vector generation, simulation, and debugging. (TetraMax, Fastscan) * Experience in Verilog coding, testbench generation & simulation * Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM) * Boundary scan Verification and test vector generation. Should have good knowledge in IEEE1149.1 and IEEE1149.6 * Basic knowledge Test-STA and constraints * Strong background on IEE1687, IJTAG, ICL and PDL * The ability to work in a multi-disciplined, cross-department environment * Solid knowledge in analog and digital circuit design, and device physics fundamentals * Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles * Excellent problem solving, debug, root cause analysis and communication skills * Strong understanding of statistical process control and data analysis techniques to drive silicon yield improvements and quality metrics * Project management capabilities to track and prioritize competing deliverables across cross-functional stakeholders including Test Engineering, Reliability, and Operations. * Experience working on ATE is a plus * Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification and silicon debug is a plus * Experience working on Tessent SSN is a plus ## Description Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production., * Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC * Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration * Responsibilities includes pattern generation & Verification at chip level, Rapid bring-up at ATE and RMA support * Working closely with STA and DI Engineers design closure for test * Generating, Verifying & Debugging Test vectors before tape release. * Validating & Debugging Test vectors on ATE during the silicon bring up phase * Assisting with silicon failure analysis, diagnostics & yield improvement efforts * Interfacing with the customer, physical design and test engineering/manufacturing teams located globally * Working closely with I/P DFT engineers & other stakeholders * Debugging customer returned parts on the ATE * Innovating newer DFT solutions to solve testability problems in 3nm & beyond * Automating DFT & Test Vector Generation flows ## Related Videos - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [The Gashlycrumb Tinies of AI Networking You Must Know (or Languish!)](https://www.wearedevelopers.com/videos/2067-the-gashlycrumb-tinies-of-ai-networking-you-must-know-or-languish) - [Building a hypercar from scratch](https://www.wearedevelopers.com/videos/607-building-a-hypercar-from-scratch) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Docker network without Docker](https://www.wearedevelopers.com/videos/1418-docker-network-without-docker) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) ## Related Articles - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers) - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Highest Paying Tech Companies for Developers](https://www.wearedevelopers.com/magazine/220-highest-paying-tech-companies-for-developers) - [Should senior developers refuse interview coding challenges?](https://www.wearedevelopers.com/magazine/29-should-senior-developers-refuse-interview-coding-challenges) - [Basic And Advanced Networking in Dart and Flutter](https://www.wearedevelopers.com/magazine/112-basic-and-advanced-networking-in-dart-and-flutter)