> Markdown version of [/jobs/ext/2932418-sr-design-verification-engineer-digital](https://www.wearedevelopers.com/jobs/ext/2932418-sr-design-verification-engineer-digital). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Sr. Design Verification Engineer - Digital - **Company:** Semtech - **Location:** San Diego, CA, United States - **Experience:** Expert - **Salary:** $130,000.0 - $200,000.0 - **Contract:** Permanent contract - **Skills:** Boolean Algebra, Computer Engineering, Continuous Integration, Microarchitecture, Software Debugging, Digital Electronics, Embedded Software, Formal Verification, Reduced Instruction Set Computing, Signal Processing, SystemVerilog, Systems Integration, Strategies of Testing, Verilog, Scripting, PIC Microcontroller, Software Verification, Physical Design - **Published:** September 16, 2026 - **Apply:** https://semtech.wd1.myworkdayjobs.com/SemtechCareers/job/USA---San-Diego-CA/Sr-Verification-Engineer---Mixed-Signal-ICs_REQ2930 ## About the Role * 8+ years of industry experience in integrated circuit design verification (DV) * In-depth knowledge and experience in digital IC verification for mixed-signal ICs with MCU based hardware systems (ARM, RISC-V, PIC, STM32) with memories, custom digital micro-architecture, interfaces, dedicated hardware peripherals, embedded signal processing, external IPs, and analog peripherals. * Proficiency in SystemVerilog as a high-level verification language with strong UVM implementation skills, Verilog for RTL comprehension and gate-level debug, Python scripting for verification automation, and industry-leading EDA verification tools (Synopsys VCS, Cadence Xcelium, Siemens Questa). * Experience with standard hardware protocols (I2C, I3C, SPI, MIPI) * Strong analytical, synthesis and problem solving skills * Demonstration of technical leadership * Independent, self-motivated, rigorous, innovating, team player and able to follow through * Excellent verbal and written communication skills * B.S. or M.S. in Electrical or Computer Engineering Desired Qualifications * Familiarity consuming analog behavioral models (SV-RNM, Verilog-AMS) provided by analog design teams to verify digital control logic and mixed-signal interfaces * Formal verification experience using JasperGold, Synopsys VC Formal, or equivalent (property checking, FSM verification, protocol compliance) * Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) sign-off experience using SpyGlass CDC, JasperGold CDC, or equivalent * Low-power verification experience including UPF/CPF for power domain management - relevant for battery-powered consumer applications * Lint and structural sign-off experience (SpyGlass Lint or equivalent) * Knowledge of system-level integration: digital hardware, embedded firmware, signal processing concepts * Experience with capacitive sensing, touch, or proximity ICs ## Description The Sr. Design Verification Engineer is responsible for developing and implementing verification plans for digital IP blocks, subsystems, and full integrated circuits within mixed-signal sensing products. The Sr. Design Verification Engineer will closely collaborate with system, digital & physical design, embedded firmware, analog, and cross functional teams. The role also includes technical leadership, mentoring and supervision of junior verification engineers, pre-silicon validation, and support to silicon validation, production test and application engineers., * Define, develop and optimize comprehensive verification plans and test strategies for digital IP blocks, subsystems, and full integrated circuits in mixed-signal products. Work closely with design teams to understand micro-architecture and functional specifications. Create and maintain detailed test plans, coverage models, and verification environments. Drive coverage closure including functional, code, and assertion-based coverage. Generate technical documentation and drive verification reviews. (30%) * Design and implement UVM testbench environments using SystemVerilog for digital IP blocks, subsystems, and full-chip verification. Perform block and chip-level RTL and gate-level verification of digital logic interfacing with analog peripherals via behavioral models provided by the analog team. Develop constrained-random verification environments, directed test cases, and reusable verification components (drivers, monitors, scoreboards, coverage models). Debug complex simulation failures and identify root causes in RTL or verification environments. Improve verification scalability and reuse across projects through environment enhancement and tool automation. Build and maintain regression infrastructure, continuous integration flows, and coverage tracking. (30%) * Interface with system, digital hardware, embedded firmware, analog and cross functional teams. (10%) * Supervise and mentor junior verification engineers. (15%) * Drive adoption of advanced verification methodologies, best practices and tool evaluation. (5%) * Support silicon lab evaluation, performance characterization and debug. (5%) * Technical support to test, product and application engineers. (5%) ## Related Videos - [JavaScript? No. Java Scripts! - Scripting with Java](https://www.wearedevelopers.com/videos/2094-javascript-no-java-scripts-scripting-with-java) - [The Billion Dollar Machine: First Time Right.](https://www.wearedevelopers.com/videos/393-the-billion-dollar-machine-first-time-right) - [Intermediate Bitcoin Script](https://www.wearedevelopers.com/videos/25-intermediate-bitcoin-script) - [When testing just doesn’t cut it](https://www.wearedevelopers.com/videos/720-when-testing-just-doesn-t-cut-it) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Oops! Stories of supply chain shenanigans](https://www.wearedevelopers.com/videos/245-oops-stories-of-supply-chain-shenanigans) ## Related Articles - [AI Eats the Verifiable First](https://www.wearedevelopers.com/magazine/765-ai-eats-the-verifiable-first) - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [How software is steering vehicle technology](https://www.wearedevelopers.com/magazine/515-how-software-is-steering-vehicle-technology) - [Why Attend a Developer Event in 2026?](https://www.wearedevelopers.com/magazine/688-why-attend-a-developer-event-in-2026) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [Highest Paying Tech Companies for Developers](https://www.wearedevelopers.com/magazine/220-highest-paying-tech-companies-for-developers)