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# Hardware Engineer (RTL / High-Level Synthesis)

- **Company:** Code
- **Location:** San Francisco, CA, United States (Remote available)
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Continuous Integration, Software Debugging, Linux, Formal Verification, Field-Programmable Gate Array (FPGA), Python (Programming Language), MATLAB, Regression Testing, Toolchain, VHSIC Hardware Description Language (VHDL), Scripting, Large Language Models, Git, Virtual Agents
- **Published:** September 16, 2026
- **Apply:** https://startup.jobs/senior-hardware-engineer-rtl-high-level-synthesis-code-metal-10080707

## About the Role

* 3+ years of hands-on experience with writing RTL code or using High-Level Synthesis, including at least one commercial HLS tool (Catapult, Vitis HLS, Stratus, or equivalent)
 * Solid hardware modeling background regarding fixed-point arithmetic, bit-accurate types, synthesis pragmas and modeling trade-offs
 * Scripting experience in Python for development, toolchain automation and testing
 * Strong debugging and problem-solving skills
 * Experience with simulation and functional verification flows

Preferred Qualifications

 * Experience using Linux-based development environments
 * Solid understanding of RTL / VHDL
 * Understanding of FPGA architectural capabilities and constraints
 * Knowledge of verification methodologies and testbench development
 * Experience with DSP algorithms and applications using Python/MATLAB

Nice to Have:

 * Bonus: Interest in or familiarity with LLM-assisted code transformation and readability tooling
 * Experience with Git-based development workflows and CI/CD environments

## Description

* Develop C++ and post-HLS readability and optimization passes to produce human-auditable RTL
 * Leveraging Agentic AI and verification capability within Code Metal
 * Contribute to CI/CD qualification including automated RTL simulation, functional verification, and regression testing


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