> Markdown version of [/jobs/ext/2983762-advanced-asic-fpga-verification-engineer-for-crypto-and-cross-do](https://www.wearedevelopers.com/jobs/ext/2983762-advanced-asic-fpga-verification-engineer-for-crypto-and-cross-do). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Advanced ASIC FPGA Verification Engineer for Crypto and Cross Do - **Company:** General Dynamics Mission Systems, Inc. - **Location:** Scottsdale, AZ, United States - **Experience:** Experienced - **Salary:** $135,396.0 - **Contract:** Permanent contract - **Skills:** Component-Based Software Engineering, Bash Shell, Code Coverage, Code Review, Computer Engineering, Continuous Integration, Software Debugging, Perl (Programming Language), Network Interface Controllers, Formal Verification, Field-Programmable Gate Array (FPGA), Github, Hardware-In-The-Loop Simulation, Python (Programming Language), Log Analysis, RSA (Cryptosystem), SystemVerilog, Tcl (Programming Language), Verilog, VHSIC Hardware Description Language (VHDL), Vivado, Scripting, Application Specific Integrated Circuits, ModelSim, Git, Gitlab-ci, Software Version Control, Jenkins - **Published:** September 18, 2026 - **Apply:** https://www.clearancejobs.com/jobs/9172250/advanced-asic-fpga-verification-engineer-for-crypto-and-cross-do ## About the Role Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience. CLEARANCE REQUIREMENTS: Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required., * Strong proficiency in SystemVerilog for verification, VHDL for verification including constrained-random stimulus, functional coverage, and assertions * Hands-on experience with UVM (Universal Verification Methodology) including environment architecture, component development, and sequence libraries * Experience with industry-standard simulation tools: QuestaSim/ModelSim Simulators * Demonstrated ability to develop verification plans, define coverage models, and drive coverage to closure * Experience with code coverage metrics (statement, branch, condition, expression, toggle) and coverage analysis workflows * Proficiency in VHDL and/or Verilog for reading and understanding design RTL * Experience with waveform debugging and signal-level analysis * Understanding of AXI-Stream, AXI4, and similar on-chip bus protocols from a verification perspective * Knowledge of clock domain crossing (CDC) verification concepts and metastability analysis * Strong written and verbal communication skills for verification plans, coverage reports, and technical presentations * S. Citizenship and ability to obtain/maintain a Secret security clearance Preferred Qualifications * Experience verifying cryptographic hardware implementations (AES, GCM, SHA, ECC, RSA, or similar) * Experience with CI/CD pipeline development and maintenance for FPGA verification (GitLab CI, GitHub Actions) -- including automated regression management, seed management, and coverage merging * Proficiency in scripting languages (Python, Tcl, Bash, Perl) for verification automation, log parsing, and results analysis * Experience with Xilinx Vivado Design Suite and FPGA-specific verification challenges (timing simulation, post-synthesis/post-route verification) * Knowledge of CDC analysis tools (Questa CDC) and lint/design rule checking tools * Experience with emulation or prototyping platforms for hardware-in-the-loop verification * Knowledge of AXI protocol specification and Questa verification IP (QVIP) usage for protocol compliance checking * Experience with version control (Git), code review processes, and collaborative development workflows ## Description * Take ownership, lead, develop and maintain UVM-based and non-UVM-based verification environments for complex FPGA designs including cryptographic engines, protocol interfaces, and system-level integration testbenches * Create comprehensive verification plans with functional coverage models, coverage goals, and closure criteria aligned to design specifications * Implement constrained-random stimulus generators, monitors, scoreboards, and functional coverage collectors using SystemVerilog, VHDL and UVM * Drive code coverage (statement, branch, condition, expression, toggle) and functional coverage to closure, analyzing coverage holes and developing targeted stimulus to fill gaps * Develop and maintain automated simulation regression suites that run across multiple test configurations and random seeds * Build and improve CI/CD pipelines for automated verification workflows -- including nightly regression runs, coverage trend tracking, and automated results reporting using Jenkins, GitLab CI, or similar platforms * Perform assertion-based verification (ABV) using SystemVerilog Assertions (SVA) to capture protocol rules, interface contracts, and design invariants * Debug complex design issues using waveform analysis (QuestaSim, Vivado), assertion failures, and coverage-driven investigation * Collaborate closely with FPGA design engineers during architecture definition to ensure designs are verification-friendly and observable * Review and contribute to design specifications, interface control documents, and verification closure reports * Mentor junior verification engineers on UVM methodology, coverage-driven verification practices, and debugging techniques * Support formal verification activities including property checking, connectivity verification, and equivalence checking where applicable ## Related Videos - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Innovating Developer Tools with AI: Insights from GitHub Next](https://www.wearedevelopers.com/videos/1268-innovating-developer-tools-with-ai-insights-from-github-next) - [How a Small Team Shrank a Microsoft Monorepo by 94%](https://www.wearedevelopers.com/videos/1236-how-a-small-team-shrank-a-microsoft-monorepo-by-94) - [Security Pitfalls for Software Engineers](https://www.wearedevelopers.com/videos/726-security-pitfalls-for-software-engineers) - [Bringing AI Model Testing and Prompt Management to Your Codebase with GitHub Models](https://www.wearedevelopers.com/videos/1536-bringing-ai-model-testing-and-prompt-management-to-your-codebase-with-github-models) - [Git for Code Reviews](https://www.wearedevelopers.com/videos/429-git-for-code-reviews) ## Related Articles - [AI Eats the Verifiable First](https://www.wearedevelopers.com/magazine/765-ai-eats-the-verifiable-first) - [How We Built a Worry-Free System That Runs for 10+ Years – And What We’d Do Again](https://www.wearedevelopers.com/magazine/751-how-we-built-a-worry-free-system-that-runs-for-10-years-and-what-we-d-do-again) - [Dev Digest 134 - Where pixels sing?](https://www.wearedevelopers.com/magazine/477-dev-digest-134-where-pixels-sing) - [9 Ways to Make Money Hacking](https://www.wearedevelopers.com/magazine/333-9-ways-to-make-money-hacking) - [Highest Paying Tech Companies for Developers](https://www.wearedevelopers.com/magazine/220-highest-paying-tech-companies-for-developers) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated)