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# Sr. ASIC RTL Design Engineer, Memory Controller

- **Company:** Tesla Motors
- **Location:** Austin, TX, United States
- **Experience:** Expert
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Computer Engineering, Microarchitecture, Software Debugging, Dynamic Random-Access Memory, Perl (Programming Language), Firmware, Field-Programmable Gate Array (FPGA), Python (Programming Language), SystemVerilog, Tcl (Programming Language), Verilog, Scripting, Application Specific Integrated Circuits, State Machines, Physical Design
- **Published:** September 22, 2026
- **Apply:** https://diversityjobs.com/candidate/trackback_apply?vacancyId=[vacid]

## About the Role

* Degree in Electrical Engineering, Computer Engineering, or equivalent experience
 * 5+ years of RTL design on complex digital IP, with direct ownership of a memory controller or high-speed memory/interface controller
 * Hands-on design experience with at least one current DRAM technology, and working knowledge of the others: LPDDR5 / LPDDR5X (LPDDR6 preferred); GDDR6 / GDDR6X (GDDR7 preferred); HBM2E / HBM3 / HBM3E (HBM4 preferred)
 * Deep understanding of DRAM internals: banks, ranks, channels, row/column timing (tRCD, tRP, tRAS, tRFC, tCCD, tWTR, tRTW), refresh, and page policy
 * Proven scheduler/arbitration and QoS work under high-bandwidth, many-outstanding, mixed-priority traffic
 * Proficiency in SystemVerilog/Verilog and scripting (Python, Perl, or Tcl)
 * Experience with AMBA host interfaces (AXI, ACE, CHI) or equivalent SoC fabrics
 * Experience with synthesis, STA, CDC, lint, and low-power design
 * Strong waveform-level debug in simulation, emulation, or silicon

## Description

You will define micro-architecture, write production RTL, close PPA, and debug silicon for LPDDR, GDDR, and/or HBM controllers on Tesla's next-generation ASICs. The work ships in cars, robots, and our training cluster.
What You'll Do

 * Own memory controller micro-architecture and RTL from spec through tape-out and silicon bring-up
 * Implement JEDEC-compliant controller logic for current DRAM generations: LPDDR5X / LPDDR6, GDDR7, and/or HBM4E
 * Design axi/CHI interface, command scheduling, bank/rank/channel arbitration, QoS, refresh, power-state machines, and read/write turnaround under mixed AI, and real-time traffic
 * Own the DFI (or equivalent) controller-PHY interface, including training, calibration, and PHY timing constraints
 * Drive bandwidth, latency, power, and area with data - not guesswork. Close the loop through synthesis, STA, and silicon measurements
 * Deliver synthesis-ready SystemVerilog that passes lint, CDC/RDC, DFT, and low-power (UPF) checks. Partner with physical design on floorplan, congestion, and timing
 * Work with architecture, PHY, verification, firmware, and post-silicon teams to close protocol, performance, and reliability issues
 * Support FPGA/emulation, first-silicon bring-up, and production debug of the memory interface
 * Write micro-architecture specs and timing documentation that other teams can execute against
 * Help define Tesla's next-generation controllers for LPDDR6, GDDR7, and HBM4, including ECC, RAS, and automotive-grade reliability


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