> Markdown version of [/jobs/ext/3030169-embedded-firmware-system-software-engineer-platform-controller-and-soc-stack](https://www.wearedevelopers.com/jobs/ext/3030169-embedded-firmware-system-software-engineer-platform-controller-and-soc-stack). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Embedded Firmware & System Software Engineer - Platform Controller and SoC Stack - **Company:** Moore's Law - **Location:** San Jose, CA, United States - **Experience:** Expert - **Contract:** Permanent contract - **Skills:** Application Programming Interfaces (APIs), Artificial Intelligence, ARM Architecture, Booting (BIOS), Computer Engineering, Data Migration, Software Debugging, Device Drivers, Firmware, PCI Express, Microsoft PowerPoint, Real-Time Operating Systems, System Software, Virtual Memory, AI Infrastructure, Network Switches, Peripherals, Information Technology - **Published:** September 22, 2026 - **Apply:** https://startup.jobs/staff-embedded-firmware-system-software-engineer-platform-controller-and-soc-stack-tylsemi-10144541 ## About the Role If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits., * 8-10 years of professional embedded firmware and/or system software development in C, with meaningful exposure to modern C++ or Rust. * Deep, hands-on RTOS experience on 32-bit microcontrollers (Arm Cortex-M or RISCV) scheduling, priority assignment, ISR design, synchronization primitives, and the failure modes each one produces. * Proven driver development experience against a formal driver model, including bus drivers and interrupt-driven peripherals. * System software fundamentals: virtual memory and address translation, DMA and cache coherency, the kernel/users pace boundary, and how a platform gets from reset vector to a running OS. * Working knowledge of PCIe architecture - enumeration, configuration space, BARs, MSI/MSI-X, and the transaction model - sufficient to debug why a device is not appearing or not moving data. * Understanding of what an IOMMU is for and what it costs: translation, isolation, and the DMA failure modes that appear when it is misconfigured. * Demonstrated ability to read a hardware specification or register map and translate it into correct, testable software without handholding. * Applied AI/ML knowledge - Strong AI based coding. * BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience., Strong candidates will have direct experience with several or some of the following. * PCIe and interconnect * IOMMU and virtualization * System software * RTOS and platform * Peripherals and subsystems ## Description There are no layers, no approval chains, no corporate theater. * If you have an idea, we test it. If it works, we ship it. * No endless meetings, no PowerPoint presentations to convince middle management., We are building the software stack that runs on next-generation silicon. Based on Zephyr-platform management controller responsible for secure boot, system software on the application processor - bootloader, kernel drivers, PCIe subsystem, and IOMMU configuration - that turns raw silicon into a platform an operating system can run on. What you'll do Firmware and platform control * Design, implement, and maintain Zephyr RTOS firmware for a platform management controllers, including device drivers, subsystem integration, and application-level services. * Write and upstream-quality-review drivers against Zephyr's driver model - devicetree bindings, Kconfig, init levels and priorities, struct device APIs. System software and high-speed interconnect * Bring up and debug PCIe links on first silicon - LTSSM progression, link training failures, lane reversal and polarity, equalization, speed and width negotiation. * Implement and maintain PCIe host controller and endpoint drivers: enumeration, configuration space, BAR allocation, MSI/MSI-X interrupt routing, AER and error handling, ASPM and link power states.