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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # SOC Micro-Architect and RTL Designer - **Company:** AGI & AGI, LLC - **Location:** Mountain View, CA, United States (Remote available) - **Experience:** Expert - **Salary:** $160,000.0 - $275,000.0 - **Contract:** Permanent contract - **Skills:** C (Programming Language), Computing Platforms, C++ (Programming Language), Code Coverage, Computer Programming, Microarchitecture, Software Debugging, Microprocessors, Memory Management, Firmware, Python (Programming Language), PCI Express, Requirements Management, Subsystems, SystemVerilog, Scripting, Graphics Processing Unit (GPU), Application Specific Integrated Circuits, Information Technology, Physical Design - **Published:** September 23, 2026 - **Apply:** https://www.careerbuilder.com/job-details/soc-micro-architect-and-rtl-designer-mountain-view-ca--df2abc46-ec56-44d2-a3e9-71724edb566b ## About the Role * Concept-to-silicon experience in driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon * 5+ years or more experience with SystemVerilog, Python, C/C++ and similar scripting and programming languages for chip design and related flows * Production-proven experience on silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed connectivity, memory management and related functionalities * Experience with testing your designs and working closely with verification teams towards performance and coverage closure goals * Hands-on experience with design synthesis, equivalence checking, design lint, clock-domain-crossing and related flows to take designs to high quality sign-off * Experience on DFT and physical design concepts and methodologies to achieve high test coverage and best-in-class timing, power and area for designs working with experts in these areas to take designs to sign-off * Familiarity with verification, emulation platforms and methodologies is a plus * Hands-on experience with participation in silicon debug and bring-up is a plus * This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week on Tuesday through Thursday Bonus Points If You Have * A huge plus if you have hands-on experience with silicon and firmware implementations of PCIe, HBM, DMA, Die-to-die subsystems., ASIC (Application Specific Integrated Circuit), Budgeting, C Programming Language, C++ Programming Language, CPU (Central Processing Unit), Clock Design, Computer Firmware, Computer Systems, DFT (Design for Test), Debugging Skills, Design Flows, Disability Insurance, GPU (Graphics Processing Unit), Health Plan, Life Insurance, Memory Management, PCI Express (PCI-E), Production Specifications, Psychiatry and Mental Health, Python Programming/Scripting Language, RTL Design, Recruiting/Staffing Agency, Reimbursement, Requirements Management, Scripting (Scripting Languages), Silicon Bringup, SystemVerilog, Team Player, Technical/Engineering Design, Test Design, Testing, Timing Verification, Training/Teaching ## Description MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. What You'll Do Here * Contribute to MatX's silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, fullchip design * Own entire subsystem or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off ready design * Plan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, area and timing closure towards various silicon milestones including design freeze and tapeout * Work closely with the verification, DFT, and physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results ## Related Videos - [Playing Pong on a shoulder press machine](https://www.wearedevelopers.com/videos/100140-playing-pong-on-a-shoulder-press-machine) - [JavaScript? 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