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# Engineer II - Digital ASIC Design

- **Company:** Microchip Technology Incorporated
- **Location:** San Jose, CA, United States
- **Experience:** Experienced
- **Salary:** $70,304.0 - $143,000.0
- **Contract:** Permanent contract
- **Skills:** Microarchitecture, Logic Synthesis of Circuits, Formal Verification, Field-Programmable Gate Array (FPGA), SystemVerilog, IEEE 802.3, Application Specific Integrated Circuits, Front End Software Development, Physical Design
- **Published:** September 23, 2026
- **Apply:** https://wd5.myworkdaysite.com/recruiting/microchiphr/External/job/CA---San-Jose---Fortune-Dr-Micrel-RD/Engineer-II---Digital-ASIC-Design_R4031-26-1

## About the Role

* 2.5 - 5 years of proven experience in ASIC or FPGA digital design.
 * BS degree in Electrical Engineering
 * Proficiency in System Verilog and a deep understanding of synchronous/asynchronous design techniques.
 * Experience with the full Cadence/Synopsys front-end EDA flow (e.g., VCS, SpyGlass, Design Compiler, PrimeTime).
 * Familiarity with PHY or Serdes protocols, knowledge of IEEE 802.3 is a plus
 * Skillful in scripts to aid efficiency
 * Post-silicon validation or bring-up experience. Proficient in lab equipment (e.g., oscilloscope, logic analyzer, ..., etc.)

## Description

* Follow the micro-architecture and implement RTL (System Verilog) of complex digital IP blocks from concept to delivery.
 * Drive Power, Performance, and Area trade-offs and optimizations to meet aggressive product targets.
 * Collaborate with SoC integration teams to ensure seamless connectivity and address top-level timing/congestion issues.
 * Lead Lint, CDC, RDC, and formal verification efforts. Work closely with Physical Design teams to close timing and resolve routing bottlenecks.
 * Cooperate with teams to verify and validate module and system functions.
 * Organize documents to record design activities.


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