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# ML Hardware Verification Manager

- **Company:** The Meta Game, Inc.
- **Location:** Sunnyvale, CA, United States
- **Experience:** Expert
- **Salary:** $212,000.0 - $294,000.0
- **Contract:** Permanent contract
- **Skills:** Artificial Intelligence, Unit Testing, Boolean Algebra, Computer Engineering, Software Debugging, Firmware, Data Flow Control, Formal Verification, Field-Programmable Gate Array (FPGA), Hardware Design, Machine Learning, SystemVerilog, Large Language Models, Convolutional Neural Networks, Information Technology, Hardware Infrastructure, Physical Design
- **Published:** September 23, 2026
- **Apply:** https://dejobs.org/x/x/F1FB69D3D11048BDA98606A528E74D4E/job/

## About the Role

10. 12+ years of experience in hardware design verification, including functional simulation, coverage-driven verification, and formal verification of digital logic
 11. 5+ years of experience in managing hardware engineering teams, including setting technical direction and driving execution across multiple concurrent projects
 12. Experience in Machine Learning on IPs and Silicon development
 13. Knowledge of SystemVerilog Assertions, X-propagation, UPF-power aware, gate-level simulations
 14. Experience with UVM-based testbench architecture and constrained-random verification methodologies applied to complex SoC or accelerator designs
 15. Experience in driving verification closure for tape-out on custom silicon, including coverage analysis, regression management, and sign-off processes
 16. Experience collaborating with RTL design, physical design, and post-silicon validation teams across the full silicon development lifecycle
 17. BS degree in Electrical Engineering, Computer Science, or relevant field, 18. Knowledge of convolutional neural networks, transformers, LLMs
 19. Master's or PhD degree in Electrical Engineering, Computer Science, or relevant field
 20. Familiarity with emulation platforms and FPGA-based prototyping as part of a pre-silicon verification flow
 21. Experience with SW/HW co-design, firmware/HW interaction testing
 22. Experience in verifying ML accelerator hardware components such as matrix multiply units, dataflow engines, or high-bandwidth memory interfaces

## Description

Meta is building custom silicon to power the next generation of AI and machine learning workloads across its Reality Labs products. We are seeking an experienced ML Hardware Verification Manager to lead the design verification efforts for custom ML accelerators and silicon platforms. In this role, you will manage a team of hardware verification engineers responsible for ensuring the functional correctness, coverage closure, and silicon readiness of ML-specific hardware designs, including tensor processing units, memory subsystems, and interconnect fabrics. You will partner closely with ML researchers, architects, RTL designers, and software teams to define verification strategies and drive tape-out milestones., 1. Lead and manage a team of hardware design verification engineers working on custom ML accelerator silicon, setting technical direction and driving execution against tape-out schedules

 2. Define and own the verification strategy for ML hardware blocks, including compute engines, memory hierarchies, and on-chip interconnects, encompassing simulation and formal verification
 3. Drive functional coverage closure and sign-off criteria across multiple silicon projects, ensuring verification completeness before tape-out
 4. Partner with RTL design and architecture teams to review specifications, identify verification risks early, and influence design-for-verifiability decisions
 5. Collaborate with post-silicon validation and software teams to align pre-silicon verification environments with bring-up and debug infrastructure
 6. Establish and scale verification infrastructure, including UVM testbench development, constrained-random stimulus generation, and assertion-based verification frameworks
 7. Translate organizational strategy into team roadmaps, balancing short-term tape-out deliverables with long-term investments in verification automation and reuse
 8. Support SW-HW co-design, development of software unit tests and/or custom kernels
 9. Communicate verification status, risk assessments, and mitigation plans clearly to engineering leadership and cross-functional stakeholders


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