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Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # Associate FPGA / ASIC Design Engineer - Summer 2027 - **Company:** MITRE Corporation - **Location:** Bedford, MA, United States - **Experience:** Starter - **Salary:** $89,200.0 - $111,500.0 - **Contract:** Temporary contract - **Skills:** Artificial Intelligence, Component-Based Software Engineering, Boolean Algebra, C++ (Programming Language), CMake, Computer Programming, Computer Engineering, Software Debugging, Logic Synthesis of Circuits, Digital Technology, Electronic Design Automation, Field-Programmable Gate Array (FPGA), Hardware Description Language, Python (Programming Language), MATLAB, Machine Learning, Rapid Prototyping Process, Signal Processing, SystemVerilog, Tcl (Programming Language), Verilog, VHSIC Hardware Description Language (VHDL), WebRTC, Scripting, Application Specific Integrated Circuits, Peripherals, SC Clearance, Build Tools, Software Defined Radio, Software Version Control, Programming Languages - **Published:** September 25, 2026 - **Apply:** https://www.clearancejobs.com/jobs/9191895/associate-fpga-asic-design-engineer-summer-2027 ## About the Role We are interested in highly motivated candidates with a wide variety of skills, insatiable curiosity, enthusiasm, and the ability and interest to dig deep on challenging technical problems. Minimum qualifications include, * Typically requires less than 1 year of related experience with a related Bachelor's degree, or equivalent combination of related education and work experience. * A Bachelor's degree in Electrical and/or Computer Engineering (or similar field), or an equivalent combination of related education and work experience. * Solid understanding of digital system design at the Boolean logic level * Solid understanding of basic circuits and electronic principles * Experience with programming and a working knowledge of one or more Hardware Description Languages (HDLs) such as VHDL, Verilog, or System Verilog * Exposure to FPGA or ASIC simulation, synthesis, and implementation tools * Exposure to programming languages such as C/C++ and Python * Strong oral and written communication skills * Applicants selected for this position will be subject to a US government security investigation and must be able to obtain and maintain a Department of Defense SECRET clearance, which requires US citizenship * Candidates must meet requirements to support project work on-site in our labs and classified facilities on the Bedford, MA Campus * This position requires a minimum of 4 days a week on-site at our Bedford, MA facility., * Master's degree in Electrical and/or Computer Engineering or similar field * Exposure to cutting-edge, reconfigurable SoC platforms (e.g., AMD Xilinx MPSoC, AMD Xilinx RFSoC, AMD Xilinx Versal, Intel Agilex SoC) * Familiarity with all phases of digital design, including architecture, implementation, verification, test, documentation, and version control * Exposure to leading edge process nodes and foundries including GlobalFoundries, Intel, and TSMC * Solid understanding of processor interface techniques such as memory mapped peripherals and interrupts * Familiarity with scripting languages and build tools (TCL, Python, CMake) * Experience deploying designs on FPGA or SDR platforms, from RTL, through simulation, synthesis, lab bring-up and debug * Fundamental understanding of microelectronic circuits and transistors * Experience in ASIC or FPGA EDA tools including synthesis, timing closure, place & route, and emulation techniques * Basic understanding of signal processing concepts and exposure to MATLAB * Familiarity with Artificial Intelligence (AI) and machine learning concepts ## Description MITRE's Electronic Systems Development department is seeking to hire talented engineers starting Summer of 2027 with a background in Field-Programmable Gate Array (FPGA) and/or Application-Specific Integrated Circuit (ASIC) design to support advanced research and development projects of national significance. Qualified candidates will join a multi-disciplinary team to help support the design and implementation of proof-of-concept prototype systems on embedded hardware platforms. Our diverse set of sponsors and research objectives provide a wide variety of interesting work opportunities such as: * Real-time communication and sensor systems leveraging cutting-edge ASIC design, FPGA technology, and Software-Defined Radio (SDR) platforms * Advanced architectures for high throughput signal processing algorithms * Tightly integrated, custom platforms targeting low size, weight, power and cost (SWaP-C) applications * Cross-disciplinary teams of similarly bright and motivated engineers on projects of national importance Roles & Responsibilities: Our team specializes in rapid prototyping of advanced sensor, communication, and navigation systems on state-of-the-art embedded system platforms. This position provides an exciting opportunity to work on the following: * Component development across FPGA and ASIC technologies * Implementation of algorithms in SW/HW on embedded systems * Development, integration, and testing of custom prototypes in the lab ## Related Videos - [Code to Road in < 12 hours](https://www.wearedevelopers.com/videos/1082-code-to-road-in-12-hours) - [More efficient software for more efficient microchips](https://www.wearedevelopers.com/videos/1164-more-efficient-software-for-more-efficient-microchips) - [Transforming Education: A Journey from interactive Markdown to Remote-Labs](https://www.wearedevelopers.com/videos/941-transforming-education-a-journey-from-interactive-markdown-to-remote-labs) - [Leveraging Large Language Models for Legacy Code Translation: Challenges and Solutions](https://www.wearedevelopers.com/videos/1157-leveraging-large-language-models-for-legacy-code-translation-challenges-and-solutions) - [Strange New Worlds: shaping the future of the digital age](https://www.wearedevelopers.com/videos/677-strange-new-worlds-shaping-the-future-of-the-digital-age) - [Hello JARVIS - Building Voice Interfaces for Your LLMS](https://www.wearedevelopers.com/videos/1641-hello-jarvis-building-voice-interfaces-for-your-llms) ## Related Articles - [Top 6 Hackathons for Developers in 2023](https://www.wearedevelopers.com/magazine/263-top-6-hackathons-for-developers-in-2023) - [Dev Digest 121 - AI goes offline](https://www.wearedevelopers.com/magazine/456-dev-digest-121-ai-goes-offline) - [How to Become an AI Engineer](https://www.wearedevelopers.com/magazine/331-how-to-become-an-ai-engineer) - [Is Software Engineering Over-Saturated?](https://www.wearedevelopers.com/magazine/418-is-software-engineering-over-saturated) - [Résumé-Driven Development: How IT trends affect the job market for software developers](https://www.wearedevelopers.com/magazine/59-resume-driven-development-how-it-trends-affect-the-job-market-for-software-developers) - [Dev Digest 166: Sycophancy, Zip bombs and AI Native Development](https://www.wearedevelopers.com/magazine/585-dev-digest-166-sycophancy-zip-bombs-and-ai-native-development)