> Markdown version of [/jobs/ext/3102133-asic-engineer-implementation-timing](https://www.wearedevelopers.com/jobs/ext/3102133-asic-engineer-implementation-timing). Every page supports `.md` or `Accept: text/markdown`. Links point to the HTML versions so they work for humans too. Agent guide: [/agents.md](https://www.wearedevelopers.com/agents.md). --- # ASIC Engineer, Implementation - Timing - **Company:** The Meta Game, Inc. - **Location:** Sunnyvale, CA, United States - **Experience:** Experienced - **Salary:** $114,000.0 - $172,000.0 - **Contract:** Permanent contract - **Skills:** Computer Engineering, Data Centers, Software Debugging, Logic Synthesis of Circuits, Perl (Programming Language), Hardware Description Language, Python (Programming Language), Static Timing Analysis, System on a Chip, SystemVerilog, Tcl (Programming Language), Scripting, Application Specific Integrated Circuits, Information Technology, Physical Design, Network Optimization - **Published:** September 27, 2026 - **Apply:** https://dejobs.org/x/x/3EAB9A02123F4BF38CCD8F7A125604EC/job/ ## About the Role 10. Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta 11. Currently has a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 12. 2+ years of experience in ASIC implementation with a focus on static timing analysis and timing closure 13. Experience with industry-standard static timing analysis and sign-off tools such as PrimeTime or equivalent 14. Experience developing and validating SDC timing constraints for complex SoC or IP designs 15. Experience with logic synthesis tools and timing-driven optimization techniques 16. Experience scripting in Python, Tcl, or Perl to automate timing analysis and reporting flows, 17. Experience with RTL design or synthesis using SystemVerilog or other hardware description languages 18. Experience with timing closure at advanced process nodes (7nm or below), including on-chip variation and multi-corner multi-mode analysis 19. Familiarity with physical design concepts such as placement, routing, and parasitic extraction as they relate to timing closure 20. Experience with clock tree synthesis and clock network optimization in the context of timing sign-off ## Description Meta's Infrastructure Silicon team is seeking an ASIC Implementation Engineer specializing in timing to help design and deliver custom silicon for data center applications. In this role, you will drive static timing analysis and timing closure across complex System on Chip designs, working at the intersection of front-end and back-end implementation to ensure our infrastructure chips meet performance, power, and area targets at advanced process nodes., 1. Develop and maintain timing constraints (SDC) for complex SoC designs, including clock definitions, input/output delays, multicycle paths, and false paths 2. Perform static timing analysis using industry-standard sign-off tools to identify and resolve setup, hold, and clock skew violations across hierarchical design blocks 3. Drive timing closure through collaboration with physical design engineers, providing guidance on placement, routing, and clock tree synthesis to meet timing targets 4. Analyze and debug timing paths across multiple clock domains, identifying critical paths and recommending RTL or physical implementation optimizations 5. Generate and validate timing reports for sign-off across process, voltage, and temperature corners, including on-chip variation analysis 6. Develop and maintain timing exception methodologies and waiver processes in coordination with design and verification teams 7. Contribute to the development and improvement of timing closure scripts and automation flows using scripting languages to increase efficiency and repeatability 8. Interface with foundry and library teams to characterize and integrate timing libraries, including standard cells, memories, and hard IP 9. Support design handoff between front-end and back-end teams by providing timing-aware synthesis netlists and constraint validation ## Related Videos - [The Sustainability Race: AI's Promises, Pitfalls and Potential](https://www.wearedevelopers.com/videos/100155-the-sustainability-race-ai-s-promises-pitfalls-and-potential) - [JavaScript? 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