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# Pcs Design Engineer

- **Company:** Hireroo
- **Location:** Barcelona, Spain
- **Contract:** Permanent contract
- **Skills:** Bash Shell, Computer Engineering, Perl (Programming Language), Ethernet, Firmware, Python (Programming Language), PCI Express, Subversion, Tcl (Programming Language), Verilog, VHSIC Hardware Description Language (VHDL), Working Model 2D, Scripting, Git, Information Technology, Physical Design
- **Published:** September 27, 2026
- **Apply:** https://www.buscojobs.com.es/pcs-design-engineer-en-barcelona-ID-373558073

## About the Role

Bachelor degree in Computer Science, Computer Engineering or related field

 - Strong experience with PCS and FEC algorithms
 - Experience with Ethernet SERDES PHY and controller integration
 - Strong Verilog experience
 - Proficiency in RTL design using Verilog or VHDL
 - Experience with timing and timing constraints
 - Experience with block level testing
 - Knowledge of scripting languages, Python, Perl, Bash or Tcl
 - Knowledge of Git or SVN
 - Experience leading teams or technical work
 - Strong problem solving skills
 - English level C1 Preferred / Valued knowledge: Experience working with RISC V architecture is highly valued, especially within processor, SoC, RTL, verification, firmware, software, PCIe, DDR, PCS, DFT, Physical Design or hardware environments.

## Description

Job Description Our client is expanding their RTL team and is looking for a Lead PCS Design Engineer with strong RTL and architecture background, focused on PCS, FEC and SERDES related Ethernet blocks.In this role, you will work in several areas of a RISC V based design for an advanced technology node.The team values vertical engineers who understand the architecture problem and can take it down to RTL implementation.Location : Barcelona, Spain - Hybrid Responsibilities: As a Lead PCS Design Engineer, your broad responsibilities will include but are not limited to:- Design and implement RTL for PCS and FEC related blocks- Work on Ethernet SERDES PHY and controller integration- Translate architecture requirements into Verilog or VHDL implementation- Work with timing constraints and design closure needs- Support block level testing- Collaborate with architecture, verification and physical design teams- Use scripting to support automation and integration- Lead technical work for PCS, FEC and SERDES related design areas- Mentor engineers and contribute to design reviews Requirements:- Bachelor degree in Computer Science, Computer Engineering or related field- Strong experience with PCS and FEC algorithms- Experience with Ethernet SERDES PHY and controller integration- Strong Verilog experience- Proficiency in RTL design using Verilog or VHDL- Experience with timing and timing constraints- Experience with block level testing- Knowledge of scripting languages, Python, Perl, Bash or Tcl- Knowledge of Git or SVN- Experience leading teams or technical work- Strong problem solving skills- English level C1 Preferred / Valued knowledge: Experience working with RISC V architecture is highly valued, especially within processor, SoC, RTL, verification, firmware, software, PCIe, DDR, PCS, DFT, Physical Design or hardware environments.What's in it for you?Our client offers an exciting, challenging role in a collaborative, dynamic environment.The right person will find many career growth opportunities in their company, whether you want to advance your technical skills or aspire to leadership in the future.Benefits: Flexible working hours(office open between 7 AM and 9 PM, employees manage their own schedule) Hybrid working model One week per year work from anywhere 25 days annual leave plus December 24 and 31 €150 per month food allowance (? €**** per year additional compensation) Private medical insurance One time relocation bonus paid with the first salary Support with housing search through an agency Visa support if required Relocation support for family Virtual shares Language classes(Spanish, English, Catalan) Tax incentive


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